View MC68HC908LD60IFU_4536303.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

m68hc08 microcontrollers freescale.com mc68hc908ld60 technical data rev. 1.1 mc68hc908ld60/d august 16, 2005

mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor technical data 3 mc68hc908ld60 technical data freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation or guarantee regarding the suitability of its products fo r any particular pu rpose, nor does freescale assume any liability arising out of the app lication or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequ ential or incidental damages. "typical" parameters which may be provided in freescale data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale product could create a situation where personal injury or death may occur. should buyer purchase or use freescale products for any such unintended or unauthorized application, buyer shall indemnify and hold free scale and its officers, employ ees, subsidiaries, affiliates, and distributors harmless against all cl aims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintend ed or unauthorized use, even if such claim alleges that freescale was negligent regarding the design or manufacture of the part. freescale, inc. is an equal opportunity/affirmative action employer. ? freescale, inc., 2001
technical data technical data mc68hc908ld60 ? rev. 1.1 4 technical data freescale semiconductor
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor list of sections 5 technical data ? mc68hc908ld60 list of sections section 1. general description . . . . . . . . . . . . . . . . . . . . 31 section 2. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . 39 section 3. random-a ccess memory (ram) . . . . . . . . . . 53 section 4. flash memory . . . . . . . . . . . . . . . . . . . . . . . . 55 section 5. configuration register (config) . . . . . . . . . 67 section 6. central processor unit (cpu) . . . . . . . . . . . . 69 section 7. oscillator (osc ) . . . . . . . . . . . . . . . . . . . . . . . 89 section 8. clock generator module (cgm) . . . . . . . . . . . 93 section 9. system integration module (sim) . . . . . . . . 107 section 10. monitor rom (mon) . . . . . . . . . . . . . . . . . . 131 section 11. timer interface module (tim) . . . . . . . . . . . 143 section 12. pulse width modulato r (pwm) . . . . . . . . . . 165 section 13. analog-to-digital converter (adc) . . . . . . 171 section 14. multi-master iic in terface (mmiic) . . . . . . . 181 section 15. ddc12ab interface . . . . . . . . . . . . . . . . . . . 195 section 16. sync processo r . . . . . . . . . . . . . . . . . . . . . . 211 section 17. input/output (i/o) port s . . . . . . . . . . . . . . . 231 section 18. external interrupt (irq ) . . . . . . . . . . . . . . . 251 section 19. keyboard interrupt module (kbi). . . . . . . . 257 section 20. computer operatin g properly (cop) . . . . 265 section 21. break module (brk) . . . . . . . . . . . . . . . . . . 271 section 22. electrical sp ecifications. . . . . . . . . . . . . . . 279 section 23. mechanical specificati ons . . . . . . . . . . . . . 287 section 24. ordering in formation . . . . . . . . . . . . . . . . . 289
list of sections technical data mc68hc908ld60 ? rev. 1.1 6 list of sections freescale semiconductor
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor table of contents 7 technical data ? mc68hc908ld60 table of contents section 1. general description 1.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 section 2. memory map 2.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3 unimplemented memory loc ations . . . . . . . . . . . . . . . . . . . . . 39 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 section 3. random-access memory (ram) 3.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 section 4. flash memory 4.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
table of contents technical data mc68hc908ld60 ? rev. 1.1 8 table of contents freescale semiconductor 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 4.4 flash control regist ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4.1 13k-byte flash even byte wr ite buffer (13kebuf) . . . . . 59 4.5 flash block erase operatio n . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4.8 flash block protecti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.8.1 flash block protect regi sters . . . . . . . . . . . . . . . . . . . . . . 64 section 5. configurat ion register (config) 5.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 5.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 section 6. central pr ocessor unit (cpu) 6.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 6.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . 77
table of contents mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor table of contents 9 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 section 7. oscillator (osc) 7.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.3 oscillator external connecti ons . . . . . . . . . . . . . . . . . . . . . . . .90 7.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 91 7.4.2 crystal amplifier out put pin (osc2) . . . . . . . . . . . . . . . . . . 91 7.4.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 91 7.4.4 external clock source (oscxclk) . . . . . . . . . . . . . . . . . . . 91 7.4.5 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.6 oscillator during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . 92 section 8. clock generator module (cgm) 8.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 8.4.1 crystal oscillator circui t . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 8.5 cgm i/o signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.5.1 external filter capac itor pin (cgmxfc) . . . . . . . . . . . . . . . 97 8.5.2 pll analog power pin (v dda) . . . . . . . . . . . . . . . . . . . . . . 97 8.5.3 pll analog ground pin (vssa). . . . . . . . . . . . . . . . . . . . . . 97 8.5.4 crystal output frequency signal (oscxclk). . . . . . . . . . . 98 8.5.5 crystal reference frequency si gnal (oscrclk). . . . . . . . 98 8.5.6 cgm base clock output (dclk1) . . . . . . . . . . . . . . . . . . . . 98 8.5.7 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . . 98
table of contents technical data mc68hc908ld60 ? rev. 1.1 10 table of contents freescale semiconductor 8.6 cgm i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.6.1 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . . 99 8.6.2 pll bandwidth control register (pbwc) . . . . . . . . . . . . . 100 8.6.3 pll programming regi ster (ppg) . . . . . . . . . . . . . . . . . . . 102 8.6.4 h & v sync output control re gister (hvocr) . . . . . . . . . 104 8.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 8.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 8.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 8.9 cgm during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . . 106 section 9. system integration module (sim) 9.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . 111 9.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.3.2 clock start-up from po r . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . 111 9.4 reset and system initiali zation. . . . . . . . . . . . . . . . . . . . . . . . 112 9.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.4.2 active resets from in ternal sources . . . . . . . . . . . . . . . . . 113 9.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 9.4.2.2 computer operati ng properly (cop) rese t. . . . . . . . . . 115 9.4.2.3 low-voltage inhibit re set . . . . . . . . . . . . . . . . . . . . . . .115 9.4.2.4 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.4.2.5 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . .116 9.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . 116 9.5.2 sim counter during stop mode re covery . . . . . . . . . . . . . 116 9.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 117 9.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 9.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
table of contents mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor table of contents 11 9.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.6.2 interrupt status regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.6.2.1 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . 123 9.6.2.2 interrupt stat us register 2 . . . . . . . . . . . . . . . . . . . . . . . 123 9.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . 124 9.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 9.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 9.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.8.1 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . 128 9.8.2 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . 129 9.8.3 sim break flag control register (sbfcr) . . . . . . . . . . . . 130 section 10. monitor rom (mon) 10.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 10.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 section 11. timer interface module (tim) 11.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
table of contents technical data mc68hc908ld60 ? rev. 1.1 12 table of contents freescale semiconductor 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 11.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 148 11.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .149 11.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 149 11.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 150 11.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 151 11.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 11.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 11.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 154 11.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 11.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.10.1 tim status and control register (tsc) . . . . . . . . . . . . . . . 155 11.10.2 tim counter regist ers (tcnth:tcntl) . . . . . . . . . . . . . . 157 11.10.3 tim counter modul o registers (tmodh:tm odl) . . . . . . 158 11.10.4 tim channel status and co ntrol registers (tsc0:tsc1) . 159 11.10.5 tim channel registers (tch0h /l:tch1h/l) . . . . . . . . . . 162 section 12. pulse width modulator (pwm) 12.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 12.4 pwm registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 12.4.1 pwm data registers 0 to 7 (0 pwm?7pwm). . . . . . . . . . . 167 12.4.2 pwm control register (pwmcr) . . . . . . . . . . . . . . . . . . . 168
table of contents mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor table of contents 13 section 13. analog-to-dig ital converter (adc) 13.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 13.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 13.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 13.4.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 13.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 13.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 13.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 13.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 13.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.7.1 adc analog power pin (vdda). . . . . . . . . . . . . . . . . . . . . 176 13.7.2 adc analog ground pin (vssa) . . . . . . . . . . . . . . . . . . . .176 13.7.3 adc voltage reference high pin (v rh) . . . . . . . . . . . . . . 176 13.7.4 adc voltage reference low pin ( vrl). . . . . . . . . . . . . . . 176 13.7.5 adc voltage in ( adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 13.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . .177 13.8.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 13.8.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . . 179 section 14. multi-master iic interface (mmiic) 14.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 14.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 14.5 multi-master iic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
table of contents technical data mc68hc908ld60 ? rev. 1.1 14 table of contents freescale semiconductor 14.5.1 multi-master iic address regist er (mmadr) . . . . . . . . . . 184 14.5.2 multi-master iic control register (mmcr) . . . . . . . . . . . . 185 14.5.3 multi-master iic ma ster control register (mimcr) . . . . . . 186 14.5.4 multi-master iic stat us register (mmsr) . . . . . . . . . . . . . 188 14.5.5 multi-master iic data transm it register (mmdtr) . . . . . . 190 14.5.6 multi-master iic data receiv e register (mmdrr ) . . . . . . 191 14.6 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . 192 section 15. ddc12ab interface 15.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 15.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 15.5 ddc protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 15.6 ddc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 15.6.1 ddc address register (dadr) . . . . . . . . . . . . . . . . . . . . . 198 15.6.2 ddc2 address register (d2adr) . . . . . . . . . . . . . . . . . . . 199 15.6.3 ddc control register (dcr) . . . . . . . . . . . . . . . . . . . . . . . 200 15.6.4 ddc master control register (d mcr) . . . . . . . . . . . . . . . 201 15.6.5 ddc status register (dsr) . . . . . . . . . . . . . . . . . . . . . . . . 204 15.6.6 ddc data transmit r egister (ddtr) . . . . . . . . . . . . . . . . 206 15.6.7 ddc data receive register (ddrr) . . . . . . . . . . . . . . . . . 207 15.7 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . 208 section 16. sync processor 16.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 16.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16.5 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 16.5.1 polarity detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
table of contents mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor table of contents 15 16.5.1.1 hsync polarity detect ion . . . . . . . . . . . . . . . . . . . . . . . . 216 16.5.1.2 vsync polarity detect ion . . . . . . . . . . . . . . . . . . . . . . . . 216 16.5.1.3 composite sync polarity detect ion . . . . . . . . . . . . . . . . 216 16.5.2 sync signal counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 16.5.3 polarity controlled hout and vout outputs . . . . . . . . . . 217 16.5.4 clamp pulse output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 16.5.5 low vertical frequency detect . . . . . . . . . . . . . . . . . . . . . 219 16.6 sync processor i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . 219 16.6.1 sync processor control & stat us register ( spcsr). . . . . 219 16.6.2 sync processor input/output control register (spiocr) . 221 16.6.3 vertical frequency registers (vfrs) . . . . . . . . . . . . . . . . . 223 16.6.4 hsync frequency registers (hfrs). . . . . . . . . . . . . . . . . . 225 16.6.5 sync processor control register 1 (spcr1). . . . . . . . . . . 227 16.6.6 h & v sync output control re gister (hvocr) . . . . . . . . . 228 16.7 system operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229 section 17. input/output (i/o) ports 17.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .231 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 17.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 17.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 17.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 236 17.3.3 port a options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 17.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 17.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 17.4.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . 239 17.4.3 port b options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 17.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 17.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 17.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . 242 17.5.3 port c options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 17.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 17.6.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 17.6.2 data direction register d. . . . . . . . . . . . . . . . . . . . . . . . . . 245
table of contents technical data mc68hc908ld60 ? rev. 1.1 16 table of contents freescale semiconductor 17.6.3 port d options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 17.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 17.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 17.7.2 data direction register e. . . . . . . . . . . . . . . . . . . . . . . . . . 249 section 18. external interrupt (irq) 18.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 18.4.1 irq pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 18.5 irq status and contro l register (intscr) . . . . . . . . . . . . . . 255 18.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 256 section 19. keyboard in terrupt module (kbi) 19.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 19.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 19.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 19.6 keyboard initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 19.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 19.7.1 keyboard status and control register. . . . . . . . . . . . . . . . 262 19.7.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 263 19.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 19.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 19.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 19.9 keyboard module during break interrupts . . . . . . . . . . . . . . . 264
table of contents mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor table of contents 17 section 20. computer op erating properly (cop) 20.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 20.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 20.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 20.4.1 oscxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 20.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 20.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 20.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 20.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 20.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 20.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 20.4.8 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 268 20.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 20.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 20.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 20.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 20.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 20.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 20.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 270 section 21. break module (brk) 21.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 21.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 21.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 21.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 274 21.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .274 21.4.3 tim during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . 274 21.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 274 21.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
table of contents technical data mc68hc908ld60 ? rev. 1.1 18 table of contents freescale semiconductor 21.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 21.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 21.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 21.6.1 break status and control register. . . . . . . . . . . . . . . . . . . 275 21.6.2 break address register s . . . . . . . . . . . . . . . . . . . . . . . . . . 276 21.6.3 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 276 21.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . . 278 section 22. electrical specifications 22.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 22.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 280 22.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 281 22.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 22.6 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 282 22.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 22.8 timer interface module characterist ics . . . . . . . . . . . . . . . . . 283 22.9 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 22.10 adc electrical characteri stics . . . . . . . . . . . . . . . . . . . . . . . . 284 22.11 sync processor timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 22.12 ddc12ab/mmiic timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 22.12.1 ddc12ab/mmiic interface input signal timing . . . . . . . . 285 22.12.2 ddc12ab/mmiic interface output signal timing . . . . . . . 285 22.13 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 286 section 23. mechanic al specifications 23.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 23.3 64-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 288
table of contents mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor table of contents 19 section 24. ordering information 24.1 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 24.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
table of contents technical data mc68hc908ld60 ? rev. 1.1 20 table of contents freescale semiconductor
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor list of figures 21 technical data ? mc68hc908ld60 list of figures figure title page 1-1 mc68hc908ld60 mcu block diagram. . . . . . . . . . . . . . . . . . 34 1-2 64-pin qfp pin assi gnment . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2-1 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2-2 control, status, and data registers . . . . . . . . . . . . . . . . . . . . .43 4-1 flash i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . 56 4-2 47,616-byte flash contro l register (flcr) . . . . . . . . . . . . . 57 4-3 13k-byte flash control register (flc r1) . . . . . . . . . . . . . . . 57 4-4 13k-byte flash even byte write buffer (13kebuf) . . . . . . . 59 4-5 flash programming flowchart . . . . . . . . . . . . . . . . . . . . . . . . 63 4-6 47,616-byte flash block protect register ( flbpr). . . . . . . . 64 4-7 13k-byte flash block protect regi ster 1 (flbpr1). . . . . . . . 64 4-8 flash block protec t start address . . . . . . . . . . . . . . . . . . . . .65 5-1 configuration register (config). . . . . . . . . . . . . . . . . . . . . . . 68 6-1 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6-2 accumulator (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6-3 index register (h:x) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6-4 stack pointer (sp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6-5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 6-6 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . 74 7-1 oscillator external connecti ons . . . . . . . . . . . . . . . . . . . . . . . .90 8-1 cgm block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8-2 cgm i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 96 8-3 pll control register (pc tl) . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8-4 pll bandwidth control register (pbwc) . . . . . . . . . . . . . . . 101
list of figures technical data mc68hc908ld60 ? rev. 1.1 22 list of figures freescale semiconductor figure title page 8-5 pll programming register (ppg) . . . . . . . . . . . . . . . . . . . . . 102 8-6 h&v sync output cont rol register (hvocr) . . . . . . . . . . . . 104 9-1 sim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 9-2 sim i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .110 9-3 osc clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9-4 external reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 9-5 internal reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9-6 sources of internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 9-7 por recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9-8 interrupt entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9-9 interrupt recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9-10 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 9-11 interrupt recognition example . . . . . . . . . . . . . . . . . . . . . . . . 120 9-12 interrupt status register 1 (int1). . . . . . . . . . . . . . . . . . . . . . 123 9-13 interrupt status register 2 (int2). . . . . . . . . . . . . . . . . . . . . . 123 9-14 wait mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9-15 wait recovery from interrupt or br eak . . . . . . . . . . . . . . . . . . 126 9-16 wait recovery from internal reset. . . . . . . . . . . . . . . . . . . . . 126 9-17 stop mode entry timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 9-18 stop mode recovery fr om interrupt or break . . . . . . . . . . . . . 127 9-19 sim break status regist er (sbsr) . . . . . . . . . . . . . . . . . . . . 128 9-20 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . . . 129 9-21 sim break flag control register (s bfcr) . . . . . . . . . . . . . . 130 10-1 monitor mode circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 10-2 monitor data format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10-3 sample monitor waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10-4 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 10-5 break transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 11-1 tim block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 11-2 pwm period and pulse wi dth . . . . . . . . . . . . . . . . . . . . . . . . 150 11-3 tim status and control register (tsc ) . . . . . . . . . . . . . . . . . 155 11-4 tim counter register s (tcnth:tcntl) . . . . . . . . . . . . . . . . 157 11-5 tim counter modulo registers (tmodh:tmodl) . . . . . . . . . 158
list of figures mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor list of figures 23 figure title page 11-6 tim channel status and contro l registers (tsc0:tsc1) . . . 159 11-7 chxmax latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 11-8 tim channel registers (tch0h/l:t ch1h/l). . . . . . . . . . . . . 163 12-1 pwm i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . 166 12-2 pwm data registers 0 to 7 (0pw m?7pwm) . . . . . . . . . . . . . 167 12-3 pwm control register (pwmcr). . . . . . . . . . . . . . . . . . . . . . 168 12-4 8-bit pwm output waveforms . . . . . . . . . . . . . . . . . . . . . . . . 169 13-1 adc i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13-2 adc block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 13-3 adc status and control register (adscr) . . . . . . . . . . . . . . 177 13-4 adc data register (adr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 13-5 adc input clock register (adiclk) . . . . . . . . . . . . . . . . . . . 179 14-1 mmiic i/o register summa ry. . . . . . . . . . . . . . . . . . . . . . . . . 183 14-2 multi-master iic address register (mmadr). . . . . . . . . . . . . 184 14-3 multi-master iic control register (mmcr). . . . . . . . . . . . . . . 185 14-4 multi-master iic master control register (mimcr) . . . . . . . . 186 14-5 multi-master iic status register (mmsr) . . . . . . . . . . . . . . . 188 14-6 multi-master iic data transmit register (mmdtr) . . . . . . . . 190 14-7 multi-master iic data receive r egister (mmdrr) . . . . . . . . 191 14-8 data transfer sequenc es for master/slave transmit/receive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 193 15-1 ddc i/o register summar y . . . . . . . . . . . . . . . . . . . . . . . . . . 197 15-2 ddc address register ( dadr) . . . . . . . . . . . . . . . . . . . . . . .198 15-3 ddc2 address register (d2adr) . . . . . . . . . . . . . . . . . . . . . 199 15-4 ddc control register ( dcr) . . . . . . . . . . . . . . . . . . . . . . . . . 200 15-5 ddc master control r egister (dmcr). . . . . . . . . . . . . . . . . . 201 15-6 ddc status register (dsr ) . . . . . . . . . . . . . . . . . . . . . . . . . . 204 15-7 ddc data transmit register (ddtr). . . . . . . . . . . . . . . . . . . 206 15-8 ddc data receive regi ster (ddrr) . . . . . . . . . . . . . . . . . . . 207 15-9 data transfer sequenc es for master/slave transmit/receive modes . . . . . . . . . . . . . . . . . . . . . . . . . . 209
list of figures technical data mc68hc908ld60 ? rev. 1.1 24 list of figures freescale semiconductor figure title page 16-1 sync processor i/o register summar y . . . . . . . . . . . . . . . . . 214 16-2 sync processor block diagram . . . . . . . . . . . . . . . . . . . . . . .215 16-3 clamp pulse output timing . . . . . . . . . . . . . . . . . . . . . . . . . . 218 16-4 sync processor control & status register (spcsr) . . . . . . . 219 16-5 sync processor input/output cont rol register (spiocr) . . . 221 16-6 vertical frequency high register . . . . . . . . . . . . . . . . . . . . . . 223 16-7 vertical frequency low register . . . . . . . . . . . . . . . . . . . . . . 223 16-8 hsync frequency high regist er . . . . . . . . . . . . . . . . . . . . . . . 225 16-9 hsync frequency low regist er . . . . . . . . . . . . . . . . . . . . . . .225 16-10 sync processor control register 1 (spcr1) . . . . . . . . . . . . . 227 16-11 h&v sync output control register (hvocr) . . . . . . . . . . . . 228 17-1 port i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .232 17-2 port a data register (pta ) . . . . . . . . . . . . . . . . . . . . . . . . . . 235 17-3 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . 236 17-4 port a i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 17-5 keyboard interrupt enable register (kier) . . . . . . . . . . . . . . 237 17-6 port b data register (ptb ) . . . . . . . . . . . . . . . . . . . . . . . . . . 238 17-7 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . 239 17-8 port b i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 17-9 pwm control register (pwmcr). . . . . . . . . . . . . . . . . . . . . . 240 17-10 port c data register (ptc ) . . . . . . . . . . . . . . . . . . . . . . . . . . 241 17-11 data direction register c (ddrc) . . . . . . . . . . . . . . . . . . . . . 242 17-12 port c i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 17-13 port d data register (ptd ) . . . . . . . . . . . . . . . . . . . . . . . . . . 244 17-14 data direction register d (ddrd) . . . . . . . . . . . . . . . . . . . . . 245 17-15 port d i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 17-16 port d control register (pdcr) . . . . . . . . . . . . . . . . . . . . . . . 247 17-17 port e data register (pte ) . . . . . . . . . . . . . . . . . . . . . . . . . . 249 17-18 data direction register e (ddre) . . . . . . . . . . . . . . . . . . . . . 249 17-19 port e i/o circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 18-1 irq module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 253 18-2 irq i/o register summary. . . . . . . . . . . . . . . . . . . . . . . . . . .253 18-3 irq status and contro l register (intscr) . . . . . . . . . . . . . . 255
list of figures mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor list of figures 25 figure title page 19-1 kbi i/o register summary . . . . . . . . . . . . . . . . . . . . . . . . . . .258 19-2 keyboard interrupt module block di agram. . . . . . . . . . . . . . . 259 19-3 keyboard status and control register (kbscr) . . . . . . . . . . 262 19-4 keyboard interrupt enable register (kbier) . . . . . . . . . . . . . 263 20-1 cop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 20-2 configuration register (config). . . . . . . . . . . . . . . . . . . . . . 268 20-3 cop control register (copctl) . . . . . . . . . . . . . . . . . . . . . . 269 21-1 break module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . 273 21-2 break module i/o register summary . . . . . . . . . . . . . . . . . . . 273 21-3 break status and control register (brkscr). . . . . . . . . . . . 275 21-4 break address register high (brkh) . . . . . . . . . . . . . . . . . . 276 21-5 break address register low (brkl) . . . . . . . . . . . . . . . . . . . 276 21-6 sim break status regist er (sbsr) . . . . . . . . . . . . . . . . . . . . 277 21-7 sim break flag control register (s bfcr) . . . . . . . . . . . . . . 278 22-1 mmiic signal timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 23-1 64-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 288
list of figures technical data mc68hc908ld60 ? rev. 1.1 26 list of figures freescale semiconductor
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor list of tables 27 technical data ? mc68hc908ld60 list of tables table title page 1-1 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 2-1 vector addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 4-1 flash memory array summary . . . . . . . . . . . . . . . . . . . . . . . 56 6-1 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6-2 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8-1 free-running hsout, vsout, de, and dclk settings . . . . 96 8-2 vco frequency multiplier (n) selectio n. . . . . . . . . . . . . . . . . 103 9-1 signal name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 9-2 pin bit set timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9-3 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 9-4 sim registers summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 10-1 monitor mode signal requirements and options . . . . . . . . . . 135 10-2 mode differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 10-3 read (read memory) command . . . . . . . . . . . . . . . . . . . . . 138 10-4 write (write memory) command. . . . . . . . . . . . . . . . . . . . . 139 10-5 iread (indexed read) co mmand . . . . . . . . . . . . . . . . . . . . . 139 10-6 iwrite (indexed write) command . . . . . . . . . . . . . . . . . . . . 140 10-7 readsp (read stack po inter) command . . . . . . . . . . . . . . . 140 10-8 run (run user program) command . . . . . . . . . . . . . . . . . . . 141 10-9 monitor baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . 141 11-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11-2 prescaler selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 11-3 mode, edge, and level selection . . . . . . . . . . . . . . . . . . . . . . 161
list of tables technical data mc68hc908ld60 ? rev. 1.1 28 list of tables freescale semiconductor table title page 12-1 pwm channels and port i/o pins. . . . . . . . . . . . . . . . . . . . . . 168 13-1 mux channel select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 13-2 adc clock divide ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 14-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 14-2 baud rate select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 15-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 15-2 baud rate select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 16-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16-2 sync output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 16-3 sync output polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 16-4 atpol, vinvo, and hinvo setting. . . . . . . . . . . . . . . . . . . .221 16-5 sample vertical frame frequencies . . . . . . . . . . . . . . . . . . . 224 16-6 clamp pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 16-7 hsync polarity detect ion pulse width . . . . . . . . . . . . . . . . . 227 16-8 atpol, vinvo, and hinvo setting. . . . . . . . . . . . . . . . . . . .228 16-9 free-running hsout, vsout, de, and dclk settings . . . 229 17-1 port control register bits summary. . . . . . . . . . . . . . . . . . . .234 17-2 port a pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 17-3 port b pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 17-4 port c pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 17-5 port d pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 17-6 port e pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 19-1 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 22-1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 280 22-2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 22-3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 22-4 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 282 22-5 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 22-6 tim characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
list of tables mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor list of tables 29 table title page 22-7 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 22-8 adc electrical characteri stics . . . . . . . . . . . . . . . . . . . . . . . . 284 22-9 sync processor timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 22-10 ddc12ab/mmiic interface input si gnal timing. . . . . . . . . . . 285 22-11 ddc12ab/mmiic interface output signal timing . . . . . . . . . 285 22-12 flash memory electrical characteri stics . . . . . . . . . . . . . . . 286 24-1 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
list of tables technical data mc68hc908ld60 ? rev. 1.1 30 list of tables freescale semiconductor
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor general description 31 technical data ? mc68hc908ld60 section 1. general description 1.1 contents 1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.4 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 1.5 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 1.2 introduction the mc68hc908ld60 is a member of the low-cost, high-performance m68hc08 family of 8-bi t microcontroller units (mcus). the m68hc08 family is based on the customer-spec ified integrated circuit (csic) design strategy. all mcus in t he family use the enhanced m68hc08 central processor unit (cpu08) and are available with a variety of modules, memory sizes and types, and package types. with special modules such as t he sync processor, analog-to-digital converter, pulse modulator module , ddc12ab interface, and multi- master iic interface, the mc68hc908ld60 is des igned specifically for use in digital monitor systems.
general description technical data mc68hc908ld60 ? rev. 1.1 32 general description freescale semiconductor 1.3 features features of the mc 68hc908ld60 mcu include the following: high-performance m68hc08 architecture fully upward-compatible objec t code with m6805, m146805, and m68hc05 families low-power design; fully st atic with stop and wait modes 3.3v operating voltage 6mhz internal bus frequency; with 24mhz external crystal 60,928 bytes of on-chip fl ash memory with security 1 feature 1,024 bytes of on-chip r andom access memory (ram) 39 general-purpose input/out put (i/o) pins, including: ? 9 dedicated i/o pins ? 30 shared-function i/o pins ? 8-bit keyboard interrupt port 2-channel, 16-bit timer interface module (tim) with selectable input capture, output com pare, and pwm capability on one channel 6-channel, 8-bit analog-to-d igital converter (adc) 8-channel, 8-bit pulse wi dth modulator (pwm) sync signal processor with the following features: ? horizontal and vertic al frequency counters ? low vertical frequency indicator (40.7hz) ? polarity controlled hsync and vsync outputs from separate sync or composite sync inputs ? internal generated fr ee-running hsync, vsync, de, and dclk ? clamp pulse output to the external pre-amp chip 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users.
general description features mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor general description 33 ddc12ab 1 module with the following: ? ddc1 hardware ? multi-master iic 2 hardware for ddc2ab; with dual address additional multi- master iic module in-system programming capability using ddc12ab communication, or standard serial link on pta0 pin system protection features: ? optional computer operati ng properly (cop) reset ? illegal opcode detection with reset ? illegal address detection with reset master reset pin (with inter nal pull-up) and power-on reset irq interrupt pin with internal pull-up and schmi tt-trigger input 64-pin quad flat pack (qfp) package features of the cpu08 include the following: enhanced hc05 programming model extensive loop control functions 16 addressing modes (eight more than the hc05) 16-bit index register and stack pointer memory-to-memory data transfers fast 8 8 multiply instruction fast 16/8 divide instruction binary-coded decimal (bcd) instructions optimization for controller applications third party c language support 1. ddc is a vesa bus standard. 2. iic is a proprietary philips interface bus.
general description technical data mc68hc908ld60 ? rev. 1.1 34 general description freescale semiconductor 1.4 mcu block diagram figure 1-1 shows the structure of the mc68hc908ld60. figure 1-1. mc68hc908l d60 mcu block diagram system integration module arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers ? 80 bytes user flash ? 60,928 bytes user ram ? 1,024 bytes monitor rom ? 1,024+464 bytes user flash vector space ? 32 bytes external irq module ddrd portd internal bus rst irq computer operating properly module ptd7/iicsda ? ptd6/iicscl ? ptd5/ddcsda ? ptd4/ddcscl ? ptd3/hout ptd2/vout clamp/tch0 power-on reset module power vss1 vdd1 vss2 vdd2 hsync ?? vsync ?? porta ddra pta7/kbi7 ptd1/de ptd0/dclk ? pin is +5v open-drain ?? pin is +5v input security module monitor mode entry module ddc12ab interface module 2-channel timer interface module multi-master iic interface module sync processor module free-run panel timing module keyboard interrupt module pulse width modulator module monitor module 8-bit analog-to-digital converter module pta0/kbi0 : portb ddrb ptb7/pwm7 ptb0/pwm0 : portc ddrc ptc5/adc5 ptc0/adc0 : ptc6 clock generator module osc1 osc2 cgmxfc 24-mhz oscillator phase-locked loop vssa vdda adc reference vrl vrh porte ddre pte7 pte0 :
general description pin assignments mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor general description 35 1.5 pin assignments figure 1-2. 64-pin qfp pin assignment pte2 pte0 ptc3/adc3 ptb5/pwm5 reserved reserved vdd1 vssa osc2 osc1 vdda pte1 pte3 pte4 pte5 pte6 pte7 cgmxfc pta3/kbi3 pta2/kbi2 pta1/kbi1 pta0/kbi0 vdd2 ptb7/pwm7 ptb6/pwm6 ptb4/pwm4 ptb3/pwm3 ptb2/pwm2 ptb1/pwm1 ptb0/pwm0 ptd7iicsda ptd6/iicscl ptd5/ddcsda ptc4/adc4 vss2 ptc5/adc5 ptc6 pta7/kbi7 pta6/kbi6 pta5/kbi5 pta4/kbi4 irq rst vrh vrl ptc0/adc0 ptc1/adc1 ptc2/adc2 vsync vss1 clamp/tch0 hsync reserved reserved reserved reserved reserved reserved reserved ptd0/dclk ptd1/de ptd2/vout ptd3/hout ptd4/ddcscl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 reserved pins should not be connected.
general description technical data mc68hc908ld60 ? rev. 1.1 36 general description freescale semiconductor 1.6 pin functions description of the pin f unctions are provided in table 1-1 . table 1-1. pin functions pin name pin description vdd1, vdd2 power supply input to the mcu. vss1, vss2 power supply ground. vdda power supply input for analog circuits. vssa power supply ground for analog circuits. osc1, osc2 connections to the on-chip oscillator. an external clock can be connected directly to osc1; with osc2 floating. see section 7. oscillator (osc) . rst external reset pin; active low; with internal pull-up and schmitt trigger input. it is driven low when any internal reset source is asserted. see section 9. system integration module (sim) . irq external irq pin; with schmitt trigger input and internal pull-up. this pin is also used for mode entry selection. see section 18. external interrupt (irq) and section 9. system integration module (sim) . cgmxfc external filter capacitor connection for the cgm module. see section 8. clock generator module (cgm) . vsync vsync input to the sync processor. this pin is rated at +5v. see section 16. sync processor . hsync hsync input to the sync processor. this pin is rated at +5v. see section 16. sync processor . pta7/kbi7?pta0/kbi0 these are shared function, bidirectional i/o port pins. each pin contains a pullup device to vdd when it is configured as an external keyboard interrupt pin. see section 17. input/output (i/o) ports and section 19. keyboard interrupt module (kbi) .
general description pin functions mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor general description 37 ptb7/pwm7?ptb0/pwm0 these are shared-function, bidirectional i/o port pins. each pin can be configured as a standard i/o pin or a pwm output channel. see section 17. input/output (i/o) ports and section 12. pulse width modulator (pwm) . vrh high voltage referenc e input to adc module. vrl low voltage reference input to adc module. ptc6 this pin is a standard bidirectional i/o pin. see section 17. input/output (i/o) ports . ptc5/adc5?ptc0/adc0 these are shared-function, bidirectional i/o port pins. each pin can be configured as a standard i/o pin or an adc input channel. see section 17. input/output (i/o) ports and section 13. analog-to- digital converter (adc) . ptd7/iicsda this is a shared-function pin. it can be configured as a standard i/o pin or the data line of the multi- master iic module. this pin is +5v open-drain when configured as output. see section 17. input/output (i/o) ports and section 14. multi-master iic interface (mmiic) . ptd6/iicscl this is a shared function pin. it can be configured as a standard i/o pin or the clock line of the multi- master iic module. this pin is +5v open-drain when configured as output. see section 17. input/output (i/o) ports and section 14. multi-master iic interface (mmiic) . ptd5/ddcsda this is a shared function pin. it can be configured as a standard i/o pin or the data line of the ddc12ab module. this pin is +5v open-drain when configured as output. see section 17. input/output (i/o) ports and section 15. ddc12ab interface . ptd4/ddcscl this is a shared function pin. it can be configured as a standard i/o pin or the clock line of the ddc12ab module. this pin is +5v open-drain when configured as output. see section 17. input/output (i/o) ports and section 15. ddc12ab interface . table 1-1. pin fun ctions (continued) pin name pin description
general description technical data mc68hc908ld60 ? rev. 1.1 38 general description freescale semiconductor note: any unused inputs and i/o ports should be tied to an appropriate logic level (either v dd or v ss ). although the i/o ports of the mc68hc908ld60 do not require termination, termination is recommended to reduce the possibility of static damage. ptd3/hout ptd2/vout ptd1/de ptd0/dclk these are shared function, bidirectional i/o port pins. these pins can be configured as standard i/o pins or free-run timing output signals. see section 17. input/output (i/o) ports and section 16. sync processor . clamp/tch0 this is shared function pins. this tim channel 0 i/o pin can be configured as the sync processor clamp output pin. see section 11. timer interface module (tim) and section 16. sync processor . pte7?pte0 these are bidirectional i/o port pins. see section 17. input/output (i/o) ports . table 1-1. pin fun ctions (continued) pin name pin description
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor memory map 39 technical data ? mc68hc908ld60 section 2. memory map 2.1 contents 2.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.3 unimplemented memory loc ations . . . . . . . . . . . . . . . . . . . . . 39 2.4 reserved memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.5 input/output (i/o) section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.2 introduction the cpu08 can address 64k-bytes of memory space. the memory map, shown in figure 2-1 , includes: 60,928 bytes of flash memory 1,024 bytes of random-a ccess memory (ram) 32 bytes of user-defined vectors 1024 + 464 bytes of monitor rom 2.3 unimplemented memory locations accessing an unimplemented locati on can cause an illegal address reset if illegal address resets are enabled. in the memory map ( figure 2-1 ) and in register figures in this document, unimplemented locations are shaded.
memory map technical data mc68hc908ld60 ? rev. 1.1 40 memory map freescale semiconductor 2.4 reserved me mory locations accessing a reserved location can hav e unpredictable effects on mcu operation. in the figure 2-1 and in register figures in this document, reserved locations are marked with the word reserv ed or with the letter r. 2.5 input/output (i/o) section most of the control, st atus, and data registers ar e in the zero page area of $0000?$007f. additional i/o registers have these addresses: $fe00; sim break st atus register, sbsr $fe01; sim reset st atus register, srsr $fe02; reserved $fe03; sim break flag control register, sbfcr $fe04; interrupt stat us register 1, int1 $fe05; interrupt stat us register 2, int2 $fe06; reserved $fe07; 47,616 bytes flash control register, flcr $fe08; 47,616 bytes flash blo ck protect register, flbpr $fe09; reserved $fe0a; 13k-bytes flash control register, flcr1 $fe0b; 13k-bytes flash blo ck protect register, flbpr1 $fe0c; break address register high, brkh $fe0d; break address register low, brkl $fe0e; break status and control register, brkscr $fe0f; reserved $ffff; cop control register, copctl data registers are shown in figure 2-2 . table 2-1 is a list of vector locations.
memory map input/output (i/o) section mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor memory map 41 $0000 i/o registers 128 bytes $007f $0080 ram 1,024 bytes $047f $0480 unimplemented 896 bytes $07ff $0800 reserved 1,024 bytes $0bff $0c00 flash memory 1,024 bytes (8 128-byte blocks) $0fff $1000 flash memory 12,288 bytes (24 512-byte blocks) $3fff $4000 flash memory 47,616 bytes (93 512-byte blocks) $f9ff $fa00 monitor rom 1,024 bytes $fdff $fe00 sim break status register (sbsr) $fe01 sim reset status register (srsr) $fe02 reserved $fe03 sim break flag control register (sbfcr) $fe04 interrupt status register 1 (int1) figure 2-1. memory map
memory map technical data mc68hc908ld60 ? rev. 1.1 42 memory map freescale semiconductor $fe05 interrupt status register 2 (int2) $fe06 reserved $fe07 47,616 bytes flash control register (flcr) $fe08 47,616 bytes flash block protect register (flbpr) $fe09 reserved $fe0a 13k-bytes flash control register (flcr1) $fe0b 13k-bytes flash protect register (flbpr1) $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and co ntrol register (brkscr) $fe0f reserved $fe10 monitor rom 464 bytes $ffdf $ffe0 flash vectors 32 bytes $ffff figure 2-1. memory map (continued)
memory map input/output (i/o) section mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor memory map 43 addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 $0006 data direction register c (ddrc) read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 data direction register e (ddre) read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 1 of 9)
memory map technical data mc68hc908ld60 ? rev. 1.1 44 memory map freescale semiconductor $000a tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $000b unimplemented read: write: reset:00000000 $000c tim counter register high (tcnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $000d tim counter register low (tcntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $000e tim counter modulo register high (tmodh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $000f tim counter modulo register low (tmodl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 $0010 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0011 tim channel 0 register high (tch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0012 tim channel 0 register low (tch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0013 tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 2 of 9)
memory map input/output (i/o) section mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor memory map 45 $0014 tim channel 1 register high (tch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0015 tim channel 1 register low (tch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0016 ddc master control register (dmcr) read: alif nakif bb mast mrw br2 br1 br0 write: reset:00000000 $0017 ddc address register (dadr) read: dad7 dad6 dad5 dad4 dad3 dad2 dad1 extad write: reset:10100000 $0018 ddc control register (dcr) read: den dien 00 txak sclien ddc1en 0 write: reset:00000000 $0019 ddc status register (dsr) read: rxif txif match srw rxak sclif txbe rxbf write: 0 0 0 reset:00001010 $001a ddc data transmit register (ddtr) read: dtd7 dtd6 dtd5 dtd4 dtd3 dtd2 dtd1 dtd0 write: reset:11111111 $001b ddc data receive register (ddrr) read: drd7 drd6 drd5 dr d4 drd3 drd2 drd1 drd0 write: reset:00000000 $001c ddc2 address register (d2adr) read: d2ad7 d2ad6 d2ad5 d2ad4 d2ad3 d2ad2 d2ad1 0 write: reset:00000000 $001d unimplemented read: write: reset: addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 3 of 9)
memory map technical data mc68hc908ld60 ? rev. 1.1 46 memory map freescale semiconductor $001e irq status and control register (intscr) read: 0000irqf0 imask mode write: ack reset:00000000 $001f configuration register (config) ? read: 0000 ssrec coprs stop copd write: reset:00000000 ? one-time writable register after each reset. $0020 $0037 reserved read: rrrrrrrr write: reset: $0038 pll control register (pctl) read: pllie pllf pllon bcs 1111 write: reset:00101111 $0039 pll bandwidth control register (pbwc) read: auto lock acq xld 0000 write: reset:00000000 $003a pll programming register (ppg) read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 $003b adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $003c adc data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: unaffected after reset $003d adc input clock register (adiclk) read: adiv2 adiv1 adiv0 00000 write: reset:00000000 $003e unimplemented read: write: reset: addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 4 of 9)
memory map input/output (i/o) section mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor memory map 47 $003f h & v sync output control register (hvocr) read: dclkph1 dclkph0 r hvocr1 hvocr0 write: reset: 00 00 $0040 sync processor control and status register (spcsr) read: vsie vedge vsif comp vinvo hinvo vpol hpol write: 0 reset:00000000 $0041 vertical frequency high register (vfhr) read: vof 0 0 vf12 vf11 vf10 vf9 vf8 write: cpw1 cpw0 reset:00000000 $0042 vertical frequency low register (vflr) read: vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 write: reset:00000000 $0043 hsync frequency high register (hfhr) read: hfh7 hfh6 hfh5 hf h4 hfh3 hfh2 hfh1 hfh0 write: reset:00000000 $0044 hsync frequency low register (hflr) read: hover 0 0 hfl4 hfl3 hfl2 hfl1 hfl0 write: reset:00000000 $0045 sync processor i/o control register (spiocr) read: vsyncs hsyncs coinvrrrbporsout write: reset:000 00 $0046 sync processor control register 1 (spcr1) read: lvsie lvsif hps1 hps0 r r atpol fshf write: 0 reset:0000 00 $0047 $004d reserved read: rrrrrrrr write: reset: $004e keyboard status and control register (kbscr) read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 5 of 9)
memory map technical data mc68hc908ld60 ? rev. 1.1 48 memory map freescale semiconductor $004f keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $0050 $0065 reserved read: rrrrrrrr write: reset: $0066 13k-byte flash even byte write buffer (13kebuf) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: unaffected after reset $0067 $0068 reserved read: rrrrrrrr write: reset: $0069 port d control register (pdcr) read: iicdate iicscle ddcdate ddcscle houte voute dee dclke write: reset:00000000 $006a multi-master iic master control register (mimcr) read: mmalif mmnakif mmbb mmast mmrw mmbr2 mmbr1 mmbr0 write: 0 0 reset:00000000 $006b multi-master iic address register (mmadr) read: mmad7 mmad6 mmad5 mmad4 mmad3 mmad2 mmad1 mmextad write: reset:10100000 $006c multi-master iic control register (mmcr) read: mmen mmien 00 mmtxak 000 write: reset:00000000 $006d multi-master iic status register (mmsr) read: mmrxif mmtxif mmatch mmsrw mmrxak 0 mmtxbe mmrxbf write: 0 0 reset:00001010 $006e multi-master iic data transmit register (mmdtr) read: mmtd7 mmtd6 mmtd5 mmtd4 mmtd3 mmtd2 mmtd1 mmtd0 write: reset:11111111 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 6 of 9)
memory map input/output (i/o) section mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor memory map 49 $006f multi-master iic data receive register (mmdrr) read: mmrd7 mmrd6 mmrd5 mmrd4 mmrd3 mmrd2 mmrd1 mmrd0 write: reset:00000000 $0070 pwm0 data register (0pwm) read: 0pwm4 0pwm3 0pwm2 0pwm1 0pwm0 0brm2 0brm1 0brm0 write: reset:00000000 $0071 pwm1 data register (1pwm) read: 1pwm4 1pwm3 1pwm2 1pwm1 1pwm0 1brm2 1brm1 1brm0 write: reset:00000000 $0072 pwm2 data register (2pwm) read: 2pwm4 2pwm3 2pwm2 2pwm1 2pwm0 2brm2 2brm1 2brm0 write: reset:00000000 $0073 pwm3 data register (3pwm) read: 3pwm4 3pwm3 3pwm2 3pwm1 3pwm0 3brm2 3brm1 3brm0 write: reset:00000000 $0074 pwm4 data register (4pwm) read: 4pwm4 4pwm3 4pwm2 4pwm1 4pwm0 4brm2 4brm1 4brm0 write: reset:00000000 $0075 pwm5 data register (5pwm) read: 5pwm4 5pwm3 5pwm2 5pwm1 5pwm0 5brm2 5brm1 5brm0 write: reset:00000000 $0076 pwm6 data register (6pwm) read: 6pwm4 6pwm3 6pwm2 6pwm1 6pwm0 6brm2 6brm1 6brm0 write: reset:00000000 $0077 pwm7 data register (7pwm) read: 7pwm4 7pwm3 7pwm2 7pwm1 7pwm0 7brm2 7brm1 7brm0 write: reset:00000000 $0078 pwm control register (pwmcr) read: pwm7e pwm6e pwm5e pwm4e pwm3e pwm2e pwm1e pwm0e write: reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 7 of 9)
memory map technical data mc68hc908ld60 ? rev. 1.1 50 memory map freescale semiconductor $0079 $007f unimplemented read: write: reset: $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 0 note: writing a logic 0 clears sbsw. $fe01 sim reset status register (srsr) read: por pin cop ilop ilad r 0 0 write: por:10000 00 $fe02 reserved read: rrrrrrrr write: reset: $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 $fe06 reserved read: rrrrrrrr write: reset: $fe07 47,616 bytes flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 8 of 9)
memory map input/output (i/o) section mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor memory map 51 $fe08 47,616 bytes flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 0 write: reset:00000000 $fe09 reserved read: rrrrrrrr write: reset: $fe0a 13k-bytes flash control register (flcr1) read: 0000 hven1 mass1 erase1 pgm1 write: reset:00000000 $fe0b 13k-bytes flash block protect register (flbpr1) read: bpr17 bpr16 bpr15 bpr14 bpr13 bpr12 bpr11 0 write: reset:00000000 $fe0c break address high register (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address low register (brkl) read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 $ffff cop control register (copctl) read: low byte of reset vector write: writing clears co p counter (any value) reset: unaffected by reset addr.register name bit 7654321bit 0 u = unaffected x = indeterminate = unimplemented r = reserved figure 2-2. control, status, a nd data register s (sheet 9 of 9)
memory map technical data mc68hc908ld60 ? rev. 1.1 52 memory map freescale semiconductor . table 2-1. vector addresses vector priority vector address vector lowest if14 $ffe0 cgm pll interrupt vector (high) $ffe1 cgm pll interrupt vector (low) if13 $ffe2 keyboard interrupt vector (high) $ffe3 keyboard interrupt vector (low) if12 $ffe4 adc interrupt vector (high) $ffe5 adc interrupt vector (low) if11 $ffe6 reserved $ffe7 reserved if10 $ffe8 mmiic vector (high) $ffe9 mmiic vector (low) if9 $ffea sync processor vector (high) $ffeb sync processor vector (low) if8 $ffec tim overflow vector (high) $ffed tim overflow vector (low) if7 $ffee tim channel 1 vector (high) $ffef tim channel 1 vector (low) if6 $fff0 tim channel 0 vector (high) $fff1 tim channel 0 vector (low) if5 $fff2 ddc12ab vector (high) $fff3 ddc12ab vector (low) if4 $fff4 reserved $fff5 reserved if3 $fff6 reserved $fff7 reserved if2 $fff8 reserved $fff9 reserved if1 $fffa irq vector (high) $fffb irq vector (low) ? $fffc swi vector (high) $fffd swi vector (low) ? $fffe reset vector (high) highest $ffff reset vector (low)
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor random-access memory (ram) 53 technical data ? mc68hc908ld60 section 3. random-access memory (ram) 3.1 contents 3.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 3.2 introduction this section describes the 1, 024 bytes of ram (random-access memory). 3.3 functional description addresses $0080 through $0 47f are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64-kbyte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page zero are 128 bytes of ra m. because the location of the stack ram is programmable, all page zero ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff out of page zero, direct addressing mode instructions can efficiently acce ss all page zero ram locations. page zero ram, therefore, provides i deal locations for frequently accessed global variables. before processing an interrupt, the cp u uses five bytes of the stack to save the contents of the cpu registers. note: for m6805 compatibility, the h register is not stacked.
random-access memory (ram) technical data mc68hc908ld60 ? rev. 1.1 54 random-access memory (ram) freescale semiconductor during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack po inter decrements during pushes and increments during pulls. note: be careful when using nested subr outines. the cpu ma y overwrite data in the ram during a s ubroutine or during the interrupt stacking operation.
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor flash memory 55 technical data ? mc68hc908ld60 section 4. flash memory 4.1 contents 4.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 4.4 flash control regist ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.4.1 13k-byte flash even byte wr ite buffer (13kebuf) . . . . . 59 4.5 flash block erase operatio n . . . . . . . . . . . . . . . . . . . . . . . . . 59 4.6 flash mass erase operation . . . . . . . . . . . . . . . . . . . . . . . . . 60 4.7 flash program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . .61 4.8 flash block protecti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 4.8.1 flash block protect regi sters . . . . . . . . . . . . . . . . . . . . . . 64 4.2 introduction this section describes the operat ion of the embedd ed flash memory. this memory can be r ead, programmed, and er ased from a single external supply. the program and er ase operations are enabled through the use of an internal charge pump.
flash memory technical data mc68hc908ld60 ? rev. 1.1 56 flash memory freescale semiconductor 4.3 functional description the mc68hc908ld60 flash memory contains two arrays: 13,312-byte array 47,616-byte array the size, address range, and me mory usage of the arrays are summarized in table 4-1 . note: an erased bit reads as logic 1 and a programmed bit reads as logic 0. addr.register name bit 7654321bit 0 $fe07 47,616 bytes flash control register (flcr) read: 0000 hven mass erase pgm write: reset:00000000 $fe08 47,616 bytes flash block protect register (flbpr) read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 0 write: reset:00000000 $fe0a 13k-bytes flash control register (flcr1) read: 0000 hven1 mass1 erase1 pgm1 write: reset:00000000 $fe0b 13k-bytes flash block protect register (flbpr1) read: bpr17 bpr16 bpr15 bpr14 bpr13 bpr12 bpr11 0 write: reset:00000000 $0066 13k-byte flash even byte write buffer (13kebuf) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: unaffected after reset figure 4-1. flash i/ o register summary table 4-1. flash memory array summary 13,312 array 47,616 array bytes 1,024 12,288 47,616 32 address range $0c00?$0fff $1000?$3fff $4000?$f9ff $ffe0?$ffff (user vectors) minimum erase size 128 bytes 512 bytes 512 bytes 32 bytes by mass erase only
flash memory flash control registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor flash memory 57 an additional 32 bytes of flash user vectors, $ffe0?$ffff, are in the same array as the 47,616-byte. each flash array is programmed and erased through control bits in thei r respective memory mapped flash control registers, flcr and flcr1. the 13k-byte array is programmed in double bytes, using the flcr1 and the even byte buffer (13kebuf). programming tools are available from freescale. contact your local freescale representative for more information. note: a security feature prevents vi ewing of the flash contents. 1 4.4 flash control registers the two flash control registers control flash pr ogram and erase operations. this register c ontrols the 47, 616-byte array: this register controls the 13k-byte array: 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users. address: $fe07 bit 7654321bit 0 read: 0000 hven mass erase pgm write: reset:00000000 = unimplemented figure 4-2. 47,616 -byte flash contro l register (flcr) address: $fe0a bit 7654321bit 0 read: 0000 hven1 mass1 erase1 pgm1 write: reset:00000000 = unimplemented figure 4-3. 13k-byte flash co ntrol register (flcr1)
flash memory technical data mc68hc908ld60 ? rev. 1.1 58 flash memory freescale semiconductor the bit definitions for flcr are the sa me for flcr1 for the other array. hven ? high-volt age enable bit this read/write bit enables the charge pump to dr ive high voltages for program and erase operati ons in the array. hv en can only be set if either pgm = 1 or erase = 1 and t he proper sequence for program or erase is followed. 1 = high voltage enabled to array and charge pump on 0 = high voltage disabled to array and charge pump off mass ? mass erase control bit this read/write bit confi gures the memory for mass erase operation or block erase operation when the erase bit is set. 1 = mass erase operation selected 0 = mass erase oper ation not selected erase ? erase control bit this read/write bit conf igures the memory for erase operation. erase is interlocked with the pgm bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = erase operation selected 0 = erase operation not selected pgm ? program control bit this read/write bit conf igures the memory fo r program operation. pgm is interlocked with the erase bit such t hat both bits cannot be equal to 1 or set to 1 at the same time. 1 = program operation selected 0 = program operation not selected note: the 13k-byte flash array is program med in double byte s. the flash control register 1 (flcr1) is used in conjunction with the 13k-byte flash even byte write buffer regi ster (13kebuf) for programming operations. see 4.4.1 13k-byte flash e ven byte write buffer (13kebuf) and 4.7 flash program operation .
flash memory flash block erase operation mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor flash memory 59 4.4.1 13k-byte flash even byte write buffer (13kebuf) bit[7:0] ? 13k-byte flash even write byte buffer data is written to this buffer to be programmed to an even location of the 13k-byte array. the byte gets programmed to the flash memory when the odd location is programm ed. even locations are $0c00, $0cde, $1000, etc; the corres ponding odd locations are $0c01, $0cdf, $1001, etc. the 13k-byte arra y are locations from $0c00 to $3fff. reset has no ef fect on these bits. 4.5 flash block erase operation the minimum erase size for the fla sh memory is one block, and is carried out by the block erase oper ation. for memory $0c00?$0fff, a block consists of 128 consecutive by tes starting from addresses $xx00 or $xx80. for memory $1000?$3fff and $4000?$f9ff, a block consists of 512 consecutive bytes starting from addresses $x000, $x200, $x400, $x600, $x800, $xa00, $xc00, or $xe00. note: the 32-byte user vector s, $ffe0?$ffff, cannot be erased by the block erase operation because of security reasons. mass erase is required to erase this block. use the following proc edure to erase a block of flash memory: 1. set the erase bit, a nd clear the mass bit in the flash control register. 2. write any data to any flash address within the block address range desired. 3. wait for a time, t nvs (min. 5 s) address: $0066 bit 76543210 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: unaffected by reset figure 4-4. 13k-byte flash even byte write buffer (13kebuf)
flash memory technical data mc68hc908ld60 ? rev. 1.1 60 flash memory freescale semiconductor 4. set the hven bit. 5. wait for a time, t erase (min. 10ms) 6. clear the erase bit. 7. wait for a time, t nvh (min. 5 s) 8. clear the hven bit. 9. after a time, t rcv (min. 1 s), the memory can be accessed again in read mode. note: programming and erasing of flash locations c annot be performed by code being executed from the same flash array that is being programmed or erased. while these operations must be performed in the order as shown, but other unrelated operati ons may occur between the steps. 4.6 flash mass erase operation a mass erase operation erases an entire array of flash memory. the mc68hc908ld60 contains two flash memory arra ys, therefore, two mass erase operations ar e required to erase a ll flash memory in the device. mass erasing the 13k-byte array, erases all flash memory from $0800 to $3fff. mass erasing the 47,616-byt e array, erases all flash memory from $4000 to $ffff. use the following proc edure to erase an entir e flash memory array: 1. set both the erase bit, and the ma ss bit in the flash control register. 2. write any data to any flash address within the flash memory address range. 3. wait for a time, t nvs (5 s). 4. set the hven bit. 5. wait for a time, t erase (10ms). 6. clear the erase bit. 7. wait for a time, t nvhl (100 s).
flash memory flash program operation mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor flash memory 61 8. clear the hven bit. 9. after time, t rcv (1 s) , the memory can be accessed again in read mode. note: programming and erasing of flash locations c annot be performed by code being executed from the same flash array that is being programmed or erased. while these operations must be performed in the order as shown, but other unrelated operati ons may occur between the steps. 4.7 flash program operation programming of the flash memory is done on a row basis. a row consists of 64 consecutive bytes starting from a ddresses $xx00, $xx40, $xx80, and $xxc0. use this step-by-s tep procedure to program a row of flash memory ( figure 4-5 is a flowchart representation): note: in order to avoid program disturbs , the row must be erased before any byte on that ro w is programmed. 1. set the pgm bit. this configur es the memory for program operation and enables the latchi ng of address and data for programming. 2. write any data to any flash address within t he row address range desired. 3. wait for a time, t nvs (min. 5 s). 4. set the hven bit. 5. wait for a time, t pgs (min. 10 s). 6. for 47,616-byte array: write data to the flash address to be programmed. for 13k-byte array: write even location data to 13kebuf then write odd location dat a to the odd flash address to be programmed. 7. wait for time, t prog (min. 20 s). 8. repeat step 6 and 7 until all the bytes within the row are programmed.
flash memory technical data mc68hc908ld60 ? rev. 1.1 62 flash memory freescale semiconductor 9. clear the pgm bit. 10. wait for time, t nvh (min. 5 s). 11. clear the hven bit. 12. after time, t rcv (min 1 s), the memory can be accessed in read mode again. this program sequence is repeated th roughout the memory until all data is programmed. note: programming and erasing of flash locations c annot be performed by code being executed from the same flash array that is being programmed or erased. while these operations must be performed in the order shown, other unrelated operations may occur between the steps. do not exceed t prog maximum. see 22.13 flash memory characteristics . 4.8 flash block protection due to the ability of the on-board charge pump to erase and program the flash memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations due to system malfunction. this protection is done by use of a flash block protect register for ea ch array (flbpr and fl bpr1). the block protect register determines t he range of the flash me mory which is to be protected. the range of t he protected area st arts from a location defined by block protect register and ends at the botto m of the flash memory array ($ffff and $3fff). when the memory is prot ected, the hven bit cannot be set in either e rase or program operations.
flash memory flash block protection mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor flash memory 63 figure 4-5. flash programming flowchart set hven bit write any data to any flash address within the row address range desired wait for a time, t nvs set pgm bit wait for a time, t pgs write data to the flash address to be programmed wait for a time, t prog clear pgm bit wait for a time, t nvh clear hven bit wait for a time, t rcv completed programming this row? y n end of programming the time between each flash address change (step 6 to step 6), or must not exceed the maximum programming time, t prog max. the time between the last flash address programmed to clearing pgm bit (step 6 to step 9) note: 1 2 3 4 5 6 7 9 10 11 12 algorithm for programming a row (64 bytes) of flash memory this row program algorithm assumes the row/s to be programmed are initially erased. write even location byte to 13k-byte flash even byte write buffer at $0066. write odd location byte to the odd flash adress to be programmed. for 47,616 bytes array for 13k-bytes array
flash memory technical data mc68hc908ld60 ? rev. 1.1 64 flash memory freescale semiconductor 4.8.1 flash block protect registers each flash block protect register is implemented as an 7-bit i/o register. the bpr bit content of the regist er determines the starting location of the protected range within the flash memory. this register c ontrols the 47, 616-byte array: this register controls the 13k-byte array: bpr[7:1] ? flash block protect bits these seven bits represent bits [ 15:9] of a 16-bit memory address. bits [8:0] are logic 0s. the resultant 16-bit address is used for specifying the start address of the flash memory for block pr otection. the flash is protected from this start address to t he end of flash memory, at $ffff. bpr1[7:1] ? flash bl ock protect bits these seven bits represent bits [ 15:9] of a 16-bit memory address. bits [8:0] are logic 0s. address: $fe08 bit 7654321bit 0 read: bpr7 bpr6 bpr5 bpr4 bpr3 bpr2 bpr1 0 write: reset:00000000 figure 4-6. 47,616-byte flash bl ock protect register (flbpr) address: $fe0b bit 7654321bit 0 read: bpr17 bpr16 bpr15 bpr14 bpr13 bpr12 bpr11 0 write: reset:00000000 figure 4-7. 13k-byte flash block pr otect register 1 (flbpr1)
flash memory flash block protection mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor flash memory 65 the resultant 16-bit address is used for specifying the start address of the flash memory for block pr otection. the flash is protected from this start address to t he end of flash memory, at $3fff. examples of block protection for 47,616-byte flash memory array: examples of block protection fo r 13k-byte flash memory array: 16-bit memory address start address of flash block protect 000000000 bpr[7:1] 0 figure 4-8. flash block protect start address bpr[7:0] flash memory protected range $40 the entire 47,616 bytes of flash memory is protected . $42 ( 0100 0010 ) $4200 ( 0100 0010 0000 0000) to $ffff $44 ( 0100 0100 ) $4400 ( 0100 0100 0000 0000) to $ffff and so on... $f8 ( 1111 1000 )$f800 ( 1111 1000 0000 0000) to $ffff $fa $ffe0 to $ffff (flash vectors) $fc $ffe0 to $ffff (flash vectors) $fe $ffe0 to $ffff (flash vectors) $00?3e the entire 47,616 bytes flash memory is not protected . bpr1[7:0] flash memory protected range $0c the entire 13k-byte flash memory is protected . $0e ( 0000 1110 ) $0e00 ( 0000 1110 0000 0000) to $3fff $10 ( 0001 0000 ) $1000 ( 0001 0000 0000 0000) to $3fff and so on... $38 ( 0011 1000 ) $3800 ( 0011 1000 0000 0000) to $3fff $3a ( 0011 1010 ) $3a00 ( 0011 1010 0000 0000) to $3fff $3c ( 0011 1100 ) $3c00 ( 0011 1100 0000 0000) to $3fff $3e ( 0011 1110 ) $3e00 ( 0011 1110 0000 0000) to $3fff $00?$0b or $40?$fe the entire 13k-byte flash memory is not protected .
flash memory technical data mc68hc908ld60 ? rev. 1.1 66 flash memory freescale semiconductor
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor configuration register (config) 67 technical data ? mc68hc908ld60 section 5. configuration register (config) 5.1 contents 5.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 5.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 5.2 introduction this section describes the config uration register , config. the configuration register enables or disables these options: stop mode recovery time (32 oscxclk cycles or 4096 oscxclk cycles) cop timeout period (2 18 ? 2 4 or 2 13 ? 2 4 oscxclk cycles) stop instruction computer operating pr operly module (cop) 5.3 functional description the configuration register is used in the initialization of various options. the configuration register can be wri tten once after each reset. all of the configuration register bits are clea red during reset. since the various options affect the operat ion of the mcu, it is recommended that this register be written immedi ately after reset. the conf iguration register is located at $001f. the configuration register may be read at anytime.
configuration register (config) technical data mc68hc908ld60 ? rev. 1.1 68 configuration register (config) freescale semiconductor 5.4 configuration register ssrec ? short stop recovery bit ssrec enables the cp u to exit stop mode with a delay of 32 oscxclk cycles instead of a 4096 oscxclk cycle delay. 1 = stop mode recovery after 32 os cxclk cycles 0 = stop mode recovery after 4096 oscxclk cycles note: exiting stop mode by pulling reset will result in the long stop recovery. if using an external crystal oscillator, do not set the ssrec bit. coprs ? cop rate select bit coprs selects the cop timeout pe riod. reset clears coprs. (see section 20. computer o perating properly (cop) .) 1 = cop timeout period = 2 13 ? 2 4 oscxclk cycles 0 = cop timeout period = 2 18 ? 2 4 oscxclk cycles stop ? stop instruction enable bit stop enables the stop instruction. 1 = stop inst ruction enabled 0 = stop instruction tr eated as illegal opcode copd ? cop disable bit copd disables the cop module. (see section 20. computer operating properly (cop) .) 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: 0 0 0 0 ssrec coprs stop copd write: reset:00000000 = unimplemented figure 5-1. configurat ion register (config)
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 69 technical data ? mc68hc908ld60 section 6. central processor unit (cpu) 6.1 contents 6.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4 cpu registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4.1 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.4.2 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.3 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.4 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.5 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.5 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 6.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 6.7 cpu during break interrupt s . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.8 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.9 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.2 introduction the m68hc08 cpu (central proce ssor unit) is an enhanced and fully object-code-compatible vers ion of the m 68hc05 cpu. the cpu08 reference manual (freescale document order number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture.
central processor unit (cpu) technical data mc68hc908ld60 ? rev. 1.1 70 central processor unit (c pu) freescale semiconductor 6.3 features object code fully upward-com patible with m68hc05 family 16-bit stack pointer with st ack manipulation instructions 16-bit index register with x-regi ster manipulation instructions 6-mhz cpu internal bus frequency 64k-byte program/data memory space 16 addressing modes memory-to-memory data moves without using accumulator fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions enhanced binary-coded decim al (bcd) data handling modular architecture with exp andable internal bu s definition for extension of addressing range beyond 64k-bytes low-power stop and wait modes 6.4 cpu registers figure 6-1 shows the five cpu registers. cpu regist ers are not part of the memory map.
central processor unit (cpu) cpu registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 71 figure 6-1. cpu registers 6.4.1 accumulator the accumulator is a general-purpose 8- bit register. the cpu uses the accumulator to hold operands and th e results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag two?s complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7654321bit 0 read: write: reset: unaffected by reset figure 6-2. accumulator (a)
central processor unit (cpu) technical data mc68hc908ld60 ? rev. 1.1 72 central processor unit (c pu) freescale semiconductor 6.4.2 index register the 16-bit index register allows i ndexed addressing of a 64k-byte memory space. h is the upper byte of the index regi ster, and x is the lower byte. h:x is the conc atenated 16-bit index register. in the indexed addressi ng modes, the cpu uses the contents of the index register to determine the conditional addr ess of the operand. the index register can serve also as a temporary data storage location. 6.4.3 stack pointer the stack pointer is a 16-bi t register that contains the address of the next location on the stack. during a rese t, the stack pointer is preset to $00ff. the reset stack pointer (rsp ) instruction sets the least significant byte to $ff and does not af fect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bi t offset and 16-bit offs et addressing modes, the stack pointer can functi on as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. bit 15 1413121110987654321 bit 0 read: write: reset:00000000 xxxxxxxx x = indeterminate figure 6-3. index register (h:x)
central processor unit (cpu) cpu registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 73 note: the location of the stack is arbitr ary and may be relocated anywhere in ram. moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, t he stack pointer must point only to ram locations. 6.4.4 program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter autom atically increm ents to the next sequential memory location every time an instruct ion or operand is fetched. jump, branch, and interr upt operations l oad the program counter with an addr ess other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vect or address is the address of the first instruction to be executed after exiti ng the reset state. 6.4.5 condition code register the 8-bit condition code register cont ains the interrupt mask and five flags that indicate the re sults of the instruction just executed. bits 6 and bit 15 1413121110987654321 bit 0 read: write: reset:0000000011111111 figure 6-4. stack pointer (sp) bit 15 1413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 6-5. prog ram counter (pc)
central processor unit (cpu) technical data mc68hc908ld60 ? rev. 1.1 74 central processor unit (c pu) freescale semiconductor 5 are set permanently to logic 1. the following paragraphs describe the functions of the cond ition code register. v ? overflow flag the cpu sets the overfl ow flag when a two's complement overflow occurs. the signed branch instructi ons bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h ? half-carry flag the cpu sets the half-carry fl ag when a carry occurs between accumulator bits 3 and 4 during an add-without-car ry (add) or add- with-carry (adc) operat ion. the half-carry flag is required for binary- coded decimal (bcd) arithmetic oper ations. the daa instruction uses the states of the h and c flags to determine t he appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 bit 7654321bit 0 read: v11hinzc write: reset:x11x1xxx x = indeterminate figure 6-6. condition code register (ccr)
central processor unit (cpu) cpu registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 75 i ? interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are ena bled when the interrupt mask is cleared. when a cpu in terrupt occurs, the interrupt mask is set automatically after t he cpu registers are sa ved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled note: to maintain m6805 family compatibility, the upper byte of the index register (h) is not sta cked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is clear ed, the highest-priority interrupt request is serviced first. a return-from-interrupt (rti) instru ction pulls the cp u registers from the stack and restores the interr upt mask from the stack. after any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (cli). n ? negative flag the cpu sets the negative flag when an arithmet ic operation, logic operation, or data manipul ation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z ? zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulati on produces a result of $00. 1 = zero result 0 = non-zero result
central processor unit (cpu) technical data mc68hc908ld60 ? rev. 1.1 76 central processor unit (c pu) freescale semiconductor c ? carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions ? such as bit test and branch, shift, and rotate ? also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 6.5 arithmetic/l ogic unit (alu) the alu performs the arit hmetic and logic operat ions defined by the instruction set. refer to the cpu08 reference manual (freescale document order number cpu08rm/ad) for a descripti on of the instructions and addressing modes and more detail about the architectu re of the cpu. 6.6 low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. 6.6.1 wait mode the wait instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. disables the cpu clock
central processor unit (cpu) cpu during break interrupts mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 77 6.6.2 stop mode the stop instruction: clears the interrupt ma sk (i bit) in the condi tion code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. afte r exit by reset, the i bit is set. disables the cpu clock after exiting stop mode, t he cpu clock begins running after the oscillator stabilization delay. 6.7 cpu during break interrupts if a break module is present on the mcu, the cpu starts a break interrupt by: loading the instruction regist er with the swi instruction loading the program counter with $fffc:$fffd or with $fefc:$fefd in monitor mode the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and retu rns the mcu to normal operation if the break interrupt has been deasserted. 6.8 instruction set summary 6.9 opcode map see table 6-2 .
central processor unit (cpu) technical data mc68hc908ld60 ? rev. 1.1 78 central processor unit (c pu) freescale semiconductor table 6-1. instr uction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a (a) + (m) + (c) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a (a) + (m) ?? ? ??? imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp (sp) + (16 ? m) ??????imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x (h:x) + (16 ? m) ??????imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a (a) & (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right ? ?? ??? dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc (pc) + 2 + rel ? (c) = 0 ? ? ? ? ? ? rel 24 rr 3 bclr n , opr clear bit n in m mn 0 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 c b0 b7 0 b0 b7 c
central processor unit (cpu) opcode map mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 79 bcs rel branch if carry bit set (same as blo) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 beq rel branch if equal pc (pc) + 2 + rel ? (z) = 1 ??????rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc (pc) + 2 + rel ? (n v ) = 0 ??????rel 90 rr 3 bgt opr branch if greater than (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 0 ??????rel 92 rr 3 bhcc rel branch if half carry bit clear pc (pc) + 2 + rel ? (h) = 0 ??????rel 28 rr 3 bhcs rel branch if half carry bit set pc (pc) + 2 + rel ? (h) = 1 ??????rel 29 rr 3 bhi rel branch if higher pc (pc) + 2 + rel ? (c) | (z) = 0 ? ? ? ? ? ? rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc (pc) + 2 + rel ? (c) = 0 ??????rel 24 rr 3 bih rel branch if irq pin high pc (pc) + 2 + rel ? irq = 1 ??????rel 2f rr 3 bil rel branch if irq pin low pc (pc) + 2 + rel ? irq = 0 ??????rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc (pc) + 2 + rel ? (z) | (n v ) = 1 ??????rel 93 rr 3 blo rel branch if lower (same as bcs) pc (pc) + 2 + rel ? (c) = 1 ??????rel 25 rr 3 bls rel branch if lower or same pc (pc) + 2 + rel ? (c) | (z) = 1 ? ? ? ? ? ? rel 23 rr 3 blt opr branch if less than (signed operands) pc (pc) + 2 + rel ? (n v ) = 1 ??????rel 91 rr 3 bmc rel branch if interrupt mask clear pc (pc) + 2 + rel ? (i) = 0 ??????rel 2c rr 3 bmi rel branch if minus pc (pc) + 2 + rel ? (n) = 1 ??????rel 2b rr 3 bms rel branch if interrupt mask set pc (pc) + 2 + rel ? (i) = 1 ??????rel 2d rr 3 bne rel branch if not equal pc (pc) + 2 + rel ? (z) = 0 ??????rel 26 rr 3 bpl rel branch if plus pc (pc) + 2 + rel ? (n) = 0 ??????rel 2a rr 3 bra rel branch always pc (pc) + 2 + rel ??????rel 20 rr 3 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) technical data mc68hc908ld60 ? rev. 1.1 80 central processor unit (c pu) freescale semiconductor brclr n , opr , rel branch if bit n in m clear pc (pc) + 3 + rel ? (mn) = 0 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc (pc) + 2 ??????rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc (pc) + 3 + rel ? (mn) = 1 ????? ? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn 1 ?????? dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc (pc) + 2; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1 pc (pc) + rel ??????rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 3 + rel ? (x) ? (m) = $00 pc (pc) + 3 + rel ? (a) ? (m) = $00 pc (pc) + 2 + rel ? (a) ? (m) = $00 pc (pc) + 4 + rel ? (a) ? (m) = $00 ?????? dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c 0 ?????0inh 98 1 cli clear interrupt mask i 0 ??0???inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m $00 a $00 x $00 h $00 m $00 m $00 m $00 0??01? dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) opcode map mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 81 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (one?s complement) m (m ) = $ff ? (m) a (a ) = $ff ? (m) x (x ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) m (m ) = $ff ? (m) 0?? ?? 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 cphx # opr cphx opr compare h:x with m (h:x) ? (m:m + 1) ? ?? ??? imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 u?? ??? inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a (a) ? 1 or m (m) ? 1 or x (x) ? 1 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 3 + rel ? (result) 0 pc (pc) + 2 + rel ? (result) 0 pc (pc) + 4 + rel ? (result) 0 ?????? dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m (m) ? 1 a (a) ? 1 x (x) ? 1 m (m) ? 1 m (m) ? 1 m (m) ? 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a (h:a)/(x) h remainder ???? ?? inh 52 7 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) technical data mc68hc908ld60 ? rev. 1.1 82 central processor unit (c pu) freescale semiconductor eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a (a m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m (m) + 1 a (a) + 1 x (x) + 1 m (m) + 1 m (m) + 1 m (m) + 1 ? ?? ?? ? dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc jump address ?????? dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc (pc) + n ( n = 1, 2, or 3) push (pcl); sp (sp) ? 1 push (pch); sp (sp) ? 1 pc unconditional address ?????? dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a (m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ( m:m + 1 ) 0?? ?? ? imm dir 45 55 ii jj dd 3 4 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x (m) 0?? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) ? ?? ??? dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0
central processor unit (cpu) opcode map mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 83 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right ? ??0 ?? dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination (m) source h:x (h:x) + 1 (ix+d, dix+) 0?? ?? ? dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a (x) (a) ?0???0inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (two?s complement) m ?(m) = $00 ? (m) a ?(a) = $00 ? (a) x ?(x) = $00 ? (x) m ?(m) = $00 ? (m) m ?(m) = $00 ? (m) ? ?? ??? dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none ? ? ? ? ? ? inh 9d 1 nsa nibble swap a a (a[3:0]:a[7:4]) ? ? ? ? ? ? inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a (a) | (m) 0 ? ? ?? ? imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp (sp) ? 1 ??????inh 87 2 pshh push h onto stack push (h); sp (sp) ? 1 ??????inh 8b 2 pshx push x onto stack push (x); sp (sp) ? 1 ??????inh 89 2 pula pull a from stack sp (sp + 1); pull ( a ) ??????inh 86 2 pulh pull h from stack sp (sp + 1); pull ( h ) ??????inh 8a 2 pulx pull x from stack sp (sp + 1); pull ( x ) ??????inh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry ? ?? ??? dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c 0 c b0 b7
central processor unit (cpu) technical data mc68hc908ld60 ? rev. 1.1 84 central processor unit (c pu) freescale semiconductor ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry ? ?? ??? dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp $ff ??????inh 9c 1 rti return from interrupt sp (sp) + 1; pull (ccr) sp (sp) + 1; pull (a) sp (sp) + 1; pull (x) sp (sp) + 1; pull (pch) sp (sp) + 1; pull (pcl) ?????? inh 80 7 rts return from subroutine sp sp + 1 ; pull ( pch) sp sp + 1; pull (pcl) ??????inh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a (a) ? (m) ? (c) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c 1 ?????1inh 99 1 sei set interrupt mask i 1 ??1???inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m (a) 0?? ?? ? dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) (h:x) 0 ? ? ?? ? dir 35 dd 4 stop enable irq pin; stop oscillator i 0; stop oscillator ? ? 0 ? ? ? inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m (x) 0?? ?? ? dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c
central processor unit (cpu) opcode map mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 85 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a (a) ? (m) ? ?? ??? imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc (pc) + 1; push (pcl) sp (sp) ? 1; push (pch) sp (sp) ? 1; push (x) sp (sp) ? 1; push (a) sp (sp) ? 1; push (ccr) sp (sp) ? 1; i 1 pch interrupt vector high byte pcl interrupt vector low byte ??1???inh 83 9 tap transfer a to ccr ccr (a) ?????? inh 84 2 tax transfer a to x x (a) ??????inh 97 1 tpa transfer ccr to a a (ccr) ? ? ? ? ? ? inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) ? $00 or (x) ? $00 or (m) ? $00 0 ? ? ?? ? dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x (sp) + 1 ??????inh 95 2 txa transfer x to a a (x) ??????inh 9f 1 txs transfer h:x to sp (sp) (h:x) ? 1 ??????inh 94 2 table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
central processor unit (cpu) technical data mc68hc908ld60 ? rev. 1.1 86 central processor unit (c pu) freescale semiconductor a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with post increment addressi ng mode rr relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offs et addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack point er 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u undefined h index register high byte v overflow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct destination addressing mode | logical or imm immediate addressing mode logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode ?( ) negation (two?s complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increm ent to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode loaded with ix1+ indexed, 8-bit offset, post increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location ? set or cleared n negative bit ? not affected table 6-1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor central processor unit (cpu) 87 central processor unit (cpu) opcode map table 6-2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789abcd9ede9eef 0 5 brset0 3dir 4 bset0 2dir 3 bra 2rel 4 neg 2dir 1 nega 1inh 1 negx 1inh 4 neg 2ix1 5 neg 3sp1 3 neg 1ix 7 rti 1inh 3 bge 2rel 2 sub 2imm 3 sub 2dir 4 sub 3ext 4 sub 3ix2 5 sub 4sp2 3 sub 2ix1 4 sub 3sp1 2 sub 1ix 1 5 brclr0 3dir 4 bclr0 2dir 3 brn 2rel 5 cbeq 3dir 4 cbeqa 3imm 4 cbeqx 3imm 5 cbeq 3ix1+ 6 cbeq 4sp1 4 cbeq 2ix+ 4 rts 1inh 3 blt 2rel 2 cmp 2imm 3 cmp 2dir 4 cmp 3ext 4 cmp 3ix2 5 cmp 4sp2 3 cmp 2ix1 4 cmp 3sp1 2 cmp 1ix 2 5 brset1 3dir 4 bset1 2dir 3 bhi 2rel 5 mul 1inh 7 div 1inh 3 nsa 1inh 2 daa 1inh 3 bgt 2rel 2 sbc 2imm 3 sbc 2dir 4 sbc 3ext 4 sbc 3ix2 5 sbc 4sp2 3 sbc 2ix1 4 sbc 3sp1 2 sbc 1ix 3 5 brclr1 3dir 4 bclr1 2dir 3 bls 2rel 4 com 2dir 1 coma 1inh 1 comx 1inh 4 com 2ix1 5 com 3sp1 3 com 1ix 9 swi 1inh 3 ble 2rel 2 cpx 2imm 3 cpx 2dir 4 cpx 3ext 4 cpx 3ix2 5 cpx 4sp2 3 cpx 2ix1 4 cpx 3sp1 2 cpx 1ix 4 5 brset2 3dir 4 bset2 2dir 3 bcc 2rel 4 lsr 2dir 1 lsra 1inh 1 lsrx 1inh 4 lsr 2ix1 5 lsr 3sp1 3 lsr 1ix 2 ta p 1inh 2 txs 1inh 2 and 2imm 3 and 2dir 4 and 3ext 4 and 3ix2 5 and 4sp2 3 and 2ix1 4 and 3sp1 2 and 1ix 5 5 brclr2 3dir 4 bclr2 2dir 3 bcs 2rel 4 sthx 2dir 3 ldhx 3imm 4 ldhx 2dir 3 cphx 3imm 4 cphx 2dir 1 tpa 1inh 2 tsx 1inh 2 bit 2imm 3 bit 2dir 4 bit 3ext 4 bit 3ix2 5 bit 4sp2 3 bit 2ix1 4 bit 3sp1 2 bit 1ix 6 5 brset3 3dir 4 bset3 2dir 3 bne 2rel 4 ror 2dir 1 rora 1inh 1 rorx 1inh 4 ror 2ix1 5 ror 3sp1 3 ror 1ix 2 pula 1inh 2 lda 2imm 3 lda 2dir 4 lda 3ext 4 lda 3ix2 5 lda 4sp2 3 lda 2ix1 4 lda 3sp1 2 lda 1ix 7 5 brclr3 3dir 4 bclr3 2dir 3 beq 2rel 4 asr 2dir 1 asra 1inh 1 asrx 1inh 4 asr 2ix1 5 asr 3sp1 3 asr 1ix 2 psha 1inh 1 ta x 1inh 2 ais 2imm 3 sta 2dir 4 sta 3ext 4 sta 3ix2 5 sta 4sp2 3 sta 2ix1 4 sta 3sp1 2 sta 1ix 8 5 brset4 3dir 4 bset4 2dir 3 bhcc 2rel 4 lsl 2dir 1 lsla 1inh 1 lslx 1inh 4 lsl 2ix1 5 lsl 3sp1 3 lsl 1ix 2 pulx 1inh 1 clc 1inh 2 eor 2imm 3 eor 2dir 4 eor 3ext 4 eor 3ix2 5 eor 4sp2 3 eor 2ix1 4 eor 3sp1 2 eor 1ix 9 5 brclr4 3dir 4 bclr4 2dir 3 bhcs 2rel 4 rol 2dir 1 rola 1inh 1 rolx 1inh 4 rol 2ix1 5 rol 3sp1 3 rol 1ix 2 pshx 1inh 1 sec 1inh 2 adc 2imm 3 adc 2dir 4 adc 3ext 4 adc 3ix2 5 adc 4sp2 3 adc 2ix1 4 adc 3sp1 2 adc 1ix a 5 brset5 3dir 4 bset5 2dir 3 bpl 2rel 4 dec 2dir 1 deca 1inh 1 decx 1inh 4 dec 2ix1 5 dec 3sp1 3 dec 1ix 2 pulh 1inh 2 cli 1inh 2 ora 2imm 3 ora 2dir 4 ora 3ext 4 ora 3ix2 5 ora 4sp2 3 ora 2ix1 4 ora 3sp1 2 ora 1ix b 5 brclr5 3dir 4 bclr5 2dir 3 bmi 2rel 5 dbnz 3dir 3 dbnza 2inh 3 dbnzx 2inh 5 dbnz 3ix1 6 dbnz 4sp1 4 dbnz 2ix 2 pshh 1inh 2 sei 1inh 2 add 2imm 3 add 2dir 4 add 3ext 4 add 3ix2 5 add 4sp2 3 add 2ix1 4 add 3sp1 2 add 1ix c 5 brset6 3dir 4 bset6 2dir 3 bmc 2rel 4 inc 2dir 1 inca 1inh 1 incx 1inh 4 inc 2ix1 5 inc 3sp1 3 inc 1ix 1 clrh 1inh 1 rsp 1inh 2 jmp 2dir 3 jmp 3ext 4 jmp 3ix2 3 jmp 2ix1 2 jmp 1ix d 5 brclr6 3dir 4 bclr6 2dir 3 bms 2rel 3 tst 2dir 1 tsta 1inh 1 tstx 1inh 3 tst 2ix1 4 tst 3sp1 2 tst 1ix 1 nop 1inh 4 bsr 2rel 4 jsr 2dir 5 jsr 3ext 6 jsr 3ix2 5 jsr 2ix1 4 jsr 1ix e 5 brset7 3dir 4 bset7 2dir 3 bil 2rel 5 mov 3dd 4 mov 2dix+ 4 mov 3imd 4 mov 2ix+d 1 stop 1inh * 2 ldx 2imm 3 ldx 2dir 4 ldx 3ext 4 ldx 3ix2 5 ldx 4sp2 3 ldx 2ix1 4 ldx 3sp1 2 ldx 1ix f 5 brclr7 3dir 4 bclr7 2dir 3 bih 2rel 3 clr 2dir 1 clra 1inh 1 clrx 1inh 3 clr 2ix1 4 clr 3sp1 2 clr 1ix 1 wait 1inh 1 txa 1inh 2 aix 2imm 3 stx 2dir 4 stx 3ext 4 stx 3ix2 5 stx 4sp2 3 stx 2ix1 4 stx 3sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb
central processor unit (cpu) technical data mc68hc908ld60 ? rev. 1.1 88 central processor unit (c pu) freescale semiconductor
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor oscillator (osc) 89 technical data ? mc68hc908ld60 section 7. oscillator (osc) 7.1 contents 7.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 7.3 oscillator external connecti ons . . . . . . . . . . . . . . . . . . . . . . . .90 7.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.4.1 crystal amplifier input pin (osc1). . . . . . . . . . . . . . . . . . . . 91 7.4.2 crystal amplifier out put pin (osc2) . . . . . . . . . . . . . . . . . . 91 7.4.3 oscillator enable signal (simoscen). . . . . . . . . . . . . . . . . 91 7.4.4 external clock source (oscxclk) . . . . . . . . . . . . . . . . . . . 91 7.4.5 oscillator out (oscout). . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.5 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 7.6 oscillator during break mode . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.2 introduction the oscillator circuit is designed for use with crystals or ceramic resonators. the oscillat or circuit generates the crystal clock signal, oscxclk, at the frequency of the crystal. this signal is divided by two before being passed on to the si m for bus clock generation. figure 7-1 shows the structure of the oscillator. the oscill ator requires various external components. the mc68hc908ld60 operates from a nominal 24mhz crystal or external clock, providing an 8mhz internal bus clock. the 24mhz clock is required for various m odules, such as the cgm.
oscillator (osc) technical data mc68hc908ld60 ? rev. 1.1 90 oscillator (osc) freescale semiconductor 7.3 oscillator ex ternal connections in its typical configur ation, the oscillator requires five external components. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 7-1 . this figure shows only the logical representat ion of the internal components and may not represent actual circui try. the oscillator conf iguration uses five components: crystal, x 1 (nominally 24mhz) fixed capacitor, c 1 tuning capacitor, c 2 (can also be a fixed capacitor) feedback resistor, r b series resistor, r s (not required for 24mhz crystal) the series resistor (r s ) is included in the diagram to follow strict pierce oscillator guidelines and may not be r equired for all rang es of operation, especially with high frequency cryst als. refer to the crystal manufacturer?s data for more information. figure 7-1. oscillator external connections c 1 c 2 simoscen oscxclk r b x 1 r s * *r s can be zero (shorted) when used with mcu from sim 2 oscout to sim to sim osc1 osc2 higher-frequency crystals. refer to manufacturer?s data. 24mhz
oscillator (osc) i/o signals mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor oscillator (osc) 91 7.4 i/o signals the following paragraphs describe the oscillator i/o signals. 7.4.1 crystal amplifier input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. an externally generated cl ock also can feed the os c1 pin of the crystal oscillator circuit. connect the exter nal clock to the o sc1 pin and let the osc2 pin float. 7.4.2 crystal amplifier output pin (osc2) the osc2 pin is the output of the crystal oscillator inverting amplifier. 7.4.3 oscillator enable signal (simoscen) the simoscen signal comes from the sim and enabl es the oscillator. 7.4.4 external clock source (oscxclk) oscxclk is the crystal oscillator out put signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 7-1 shows only the logical rela tion of oscxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of oscxclk is unknown and may d epend on the crystal and other external factors. also, the frequen cy and amplitude of oscxclk can be unstable at start-up. 7.4.5 oscillator out (oscout) the clock driven to the si m is the crystal frequency divided by two. this signal is driven to the sim for genera tion of the bus clocks used by the cpu and other modules on the mcu. oscout will be divided again in the sim and results in th e internal bus frequency being one four th of the oscxclk frequency.
oscillator (osc) technical data mc68hc908ld60 ? rev. 1.1 92 oscillator (osc) freescale semiconductor 7.5 low power modes the wait and stop in structions put the mcu in low-power- consumption standby modes. 7.5.1 wait mode the wait instruction has no effect on the osci llator logic. oscxclk continues to drive to the sim module. 7.5.2 stop mode the stop instructio n disables the oscxclk output. 7.6 oscillator during break mode the oscillator continues drive oscxclk when the ch ip enters the break state.
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 93 technical data ? mc68hc908ld60 section 8. clock generator module (cgm) 8.1 contents 8.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 8.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 8.4.1 crystal oscillator circui t . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 8.5 cgm i/o signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 8.5.1 external filter capac itor pin (cgmxfc) . . . . . . . . . . . . . . . 97 8.5.2 pll analog power pin (v dda) . . . . . . . . . . . . . . . . . . . . . . 97 8.5.3 pll analog ground pin (vssa). . . . . . . . . . . . . . . . . . . . . . 97 8.5.4 crystal output frequency signal (oscxclk). . . . . . . . . . . 98 8.5.5 crystal reference frequency si gnal (oscrclk). . . . . . . . 98 8.5.6 cgm base clock output (dclk1) . . . . . . . . . . . . . . . . . . . . 98 8.5.7 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . . 98 8.6 cgm i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 8.6.1 pll control register (pctl) . . . . . . . . . . . . . . . . . . . . . . . . 99 8.6.2 pll bandwidth control register (pbwc) . . . . . . . . . . . . . 100 8.6.3 pll programming regi ster (ppg) . . . . . . . . . . . . . . . . . . . 102 8.6.4 h & v sync output control re gister (hvocr) . . . . . . . . . 104 8.7 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 8.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 8.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 8.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 8.9 cgm during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . . 106
clock generator module (cgm) technical data mc68hc908ld60 ? rev. 1.1 94 clock generator module (cgm) freescale semiconductor 8.2 introduction this section describes the clock generator m odule (cgm). using the crystal reference clock from the o scillator module, the cgm generates the display base clock, dclk1, for the sync processor module. the cgm is able to generate a frequen cy up to 108mhz from a 24mhz reference clock. 8.3 features features of the cgm include the following: phase-locked loop with output freque ncy in integer multiples of the crystal reference programmable hardware voltage-c ontrolled oscillator (vco) for low-jitter operation automatic bandwidth control mode for low-jitt er operation automatic frequency lock detector cpu interrupt on entry or exit from locked condition 8.4 functional description the cgm consists of th ree major sub-modules: crystal oscillator circuit which generates the buffered constant crystal frequency cl ock, oscrclk. (see section 7. oscillator (osc) .) phase-locked loop (p ll) which generates the programmable vco frequency clock cgmvclk. base clock selector ci rcuit; this software-controlled circuit selects either oscxclk divided by tw o or the vco clock cgmvclk divided by two, as the base clock dclk1. the sync processor derives other display clocks from dclk1.
clock generator module (cgm) functional description mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 95 figure 8-1. cgm block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator lock detector clock oscxclk cgmvdv simoscen oscillator (osc) interrupt control cgmint cgmrdv pll analog oscrclk osc2 osc1 select circuit v dda cgmxfc v ssa lock auto acq pllie pllf mul[7:4] reference divider vrs[7:4] (to sim) (to sim) hvocr[1:0] (from sim) cgmvclk phase-locked loop (pll) dclk1 bandwidth control (to sync processor) (see section 7. oscillator (osc) .) oscout 2 n l
clock generator module (cgm) technical data mc68hc908ld60 ? rev. 1.1 96 clock generator module (cgm) freescale semiconductor addr.register name bit 7654321bit 0 $0038 pll control register (pctl) read: pllie pllf pllon bcs 1111 write: reset:00101111 $0039 pll bandwidth control register (pbwc) read: auto lock acq xld 0000 write: reset:00000000 $003a pll programming register (ppg) read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 $003f h&v sync output control register (hvocr) read: dclkph1 dclkph0 r hvocr1 hvocr0 write: reset: 00 00 = unimplemented r = reserved notes: 1. when auto = 0, pllie is forced to logic zero and is read-only. 2. when auto = 0, pllf and lock read as logic zero. 3. when auto = 1, acq is read-only. 4. when pllon = 0 or vrs[7:4] = $0, bcs is forced to logic zero and is read-only. 5. when pllon = 1, the pll programming register is read-only. 6. when bcs = 1, pllon is forced set and is read-only. figure 8-2. cgm i/o register summary table 8-1. free-running hsout, vsout, de, and dclk settings register settings output pin video modes hvocr[1:0] mul[7:4] vrs[7:4] hout frequency vout frequency dclk frequency de video mode 00 3 3 31.45khz 59.91hz 24mhz vga 640 480 01 5 3 37.87khz 60.31hz 40mhz svga 800 600 10 8 6 48.37khz 60.31hz 64mhz xga 1024 768 11 9 9 64.32khz 60.00hz 108mhz sxga 1280 1024
clock generator module (cgm) cgm i/o signals mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 97 8.4.1 crystal oscillator circuit the crystal oscillator circuit consis ts of an inverting amplifier and an external crystal. the osc1 pin is t he input to the amp lifier and the osc2 pin is the output. the simoscen si gnal from the sys tem integration module (sim) enables the cr ystal oscillator circuit. the oscxclk signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. oscxcl k is then buffered to produce oscrclk, the pll reference clock. (see section 7. oscillator (osc) .) 8.5 cgm i/o signals the following paragraphs descr ibe the cgm i/o signals. 8.5.1 external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to fi lter out phase corrections. a small external capacitor (c f ) is connected to this pin. note: to prevent noise problems, c f should be placed as close to the cgmxfc pin as possible, with minimum routing distances and no routing of other si gnals across the c f connection. 8.5.2 pll analog power pin (vdda) vdda is the power pin used by the a nalog portions of the pll. the pin should be connected to the same voltage pot ential as the vdd pin. 8.5.3 pll analog ground pin (vssa) vssa is the ground pin us ed by the analog portions of the pll. the pin should be connected to the same voltage pot ential as the vss pin. note: route vdda and vssa carefully for maximum noise immunity and place bypass capacitors as cl ose as possible to the package.
clock generator module (cgm) technical data mc68hc908ld60 ? rev. 1.1 98 clock generator module (cgm) freescale semiconductor 8.5.4 crystal output frequency signal (oscxclk) oscxclk is the crystal oscillator out put signal. it runs at the full speed of the crystal (f xclk ) and is generated di rectly from the crystal oscillator circuit. the duty cycle of oscxc lk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of oscxclk can be unstab le at start-up. 8.5.5 crystal reference frequency signal (oscrclk) oscrclk is the buffered version of oscxclk. it runs at the full speed of the crystal (f xclk ) and provides the refer ence for the pll circuit. 8.5.6 cgm base clock output (dclk1) dclk1 is the clock output of the cg m. this signal goes to the sync processor, which generates the di splay clocks. dclk1 is software programmable to be eith er the oscillator output (oscxclk) or the vco clock (cgmvclk). 8.5.7 cgm cpu interrupt (cgmint) cgmint is the interrupt signal generated by the pll lock detector. 8.6 cgm i/o registers the following registers control and monitor operation of the cgm: pll control r egister (pctl) pll bandwidth cont rol register (pbwc) pll programming register (ppg) h & v sync output co ntrol register (hvocr)
clock generator module (cgm) cgm i/o registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 99 8.6.1 pll control register (pctl) the pll control register contains t he interrupt enable a nd flag bits, the on/off switch, and the base clock selector bit. pllie ? pll interrupt enable bit this read/write bi t enables the pll to gener ate an interrupt request when the lock bit toggles, sett ing the pll flag, pllf. when the auto bit in the pll bandwidth c ontrol register (pbwc) is clear, pllie cannot be written and reads as 0. reset clears the pllie bit. 1 = pll interrupts enabled 0 = pll interrupts disabled pllf ? pll interrupt flag bit this read-only bit is set wheneve r the lock bit toggles. pllf generates an interrupt request if th e pllie bit is set also. pllf always reads as 0 when the auto bi t in the pll bandwidth control register (pbwc) is clear. the pllf bit should be cleared by reading the pll control register. reset clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition note: the pllf bit shoul d not be inadvertently cl eared. any read or read- modify-write operation on the pll cont rol register clear s the pllf bit. address: $0038 bit 7654321bit 0 read: pllie pllf pllon bcs 1111 write: reset:00101111 = unimplemented figure 8-3. pll cont rol register (pctl)
clock generator module (cgm) technical data mc68hc908ld60 ? rev. 1.1 100 clock generator module (cgm) freescale semiconductor pllon ? pll on bit this read/write bit activates t he pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving the base clock, dclk1 (bcs = 1). reset se ts this bit so that the loop can stabilize as the mcu is powering up. 1 = pll on 0 = pll off bcs ? base clock select bit this read/write bit sele cts either the crystal oscillator output, oscxclk, or the vco cl ock, cgmvclk, as t he source of the cgm output, dclk1. bcs canno t be set while the pllo n bit is clear. after toggling bcs, it may take up to three oscxc lk and three cgmvclk cycles to complete the transition fr om one source clock to the other. during the transition, dclk1 is held in stas is. reset and the stop instruction clear the bcs bit. 1 = dclk1 driven by cgmvclk 0 = dclk1 driven by oscxclk note: pllon and bcs have built-in protec tion that prevents the base clock selector circuit from se lecting the vco clock as the source of the base clock if the pll is of f. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is clear. if the pll is off (pllon = 0), selecting cgmvclk require s two writes to the pll control register. 8.6.2 pll bandwidth control register (pbwc) the pll bandwidth control regi ster does the following: selects automatic or manual (software-controlled) bandwidth control mode indicates when the pll is locked in automatic bandwidth control mode , indicates when the pll is in acquisition or tracking mode in manual operation, forces the pll into acquisition or tracking mode
clock generator module (cgm) cgm i/o registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 101 auto ? automatic bandwidth control bit this read/write bit sele cts automatic or manual bandwidth control. when initializing the p ll for manual operation (auto = 0), the acq bit should be cleared before turni ng the pll on. reset clears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock ? lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock cgmvclk, is locked (running at the programmed frequency). when the au to bit is clear, lock reads as 0 and has no me aning. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency inco rrect or unlocked acq ? acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tr acking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisiti on or tracking mode. in automatic bandwidth control mode (auto = 1), the last-written value from manual operati on is stored in a te mporary location and is recovered when manual oper ation resumes. rese t clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode address: $0039 bit 7654321bit 0 read: auto lock acq xld 0000 write: reset:00000000 = unimplemented figure 8-4. pll bandwidth control register (pbwc)
clock generator module (cgm) technical data mc68hc908ld60 ? rev. 1.1 102 clock generator module (cgm) freescale semiconductor xld ? crystal loss detect bit when the vco output, cgm vclk, is driving dclk1, this read/write bit indicates whether the crystal reference frequency is active or not. to check the status of the crystal reference, the following procedure should be followed: 1. write a 1 to xld. 2. wait 4 n cycles. (n is the vco freque ncy multiplier, mul[7:4].) 3. read xld. 1 = crystal refere nce is not active 0 = crystal reference is active the crystal loss detect function wor ks only when the bcs bit is set, selecting cgmvclk to drive dclk1. when bcs is clear, xld always reads as 0. bits [3:0] ? reserved for test these bits enable test functions not available in user mode. to ensure software portability fr om development systems to user applications, software should write zeros to bits [3:0] whenever writing to pbwc. 8.6.3 pll programming register (ppg) the pll programming regist er contains the program ming information for the modulo feedback divider and the programming information for the hardware configurat ion of the vco. address: $003a bit 7654321bit 0 read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset:01100110 figure 8-5. pll program ming register (ppg)
clock generator module (cgm) cgm i/o registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 103 mul[7:4] ? multip lier select bits these read/write bits control the m odulo feedback divider that selects the vco frequency multiplier, n. a value of $0 in the multiplier select bits configures the m odulo feedback divider th e same as a value of $1. reset initializes these bits to $6 to give a defaul t multiply value of 6. note: the multiplier select bits have built-in protection that prevents them from being written when the p ll is on (pllon = 1). vrs[7:4] ? vco r ange select bits these read/write bits control the hardware center-of-range linear multiplier l, which controls the hardware cent er-of-range frequency f vrs . vrs[7:4] cannot be written wh en the pllon bit in the pll control register (pctl) is set. a va lue of $0 in the vco range select bits disables the pll and clears the bcs bit in the pctl. reset initializes the bits to $6 to give a default range mult iply value of 6. note: the vco range select bits have built-i n protection that prevents them from being written when the pll is on (p llon = 1) and prevents selection of the vco clo ck as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the vco range select bits must be programmed correctly. incorrect programming may result in failur e of the pll to achieve lock. table 8-2. vco frequency mu ltiplier (n) selection mul7:mul6:mul5:mul4 vco frequency multiplier (n) 0000 1 0001 1 0010 2 0011 3 1101 13 1110 14 1111 15
clock generator module (cgm) technical data mc68hc908ld60 ? rev. 1.1 104 clock generator module (cgm) freescale semiconductor 8.6.4 h & v sync output control register (hvocr) the h&v sync output control register controls the pll reference input prescaler and the final free-running waveforms for the sync processor output signals on hout, vo ut, dclk, and de pins. (see section 16. sync processor .) dclkph[1:0] ? dclk output phase adjustment these two bits are programmed to adjust the dclk output phase. each increment add s approximately 2 to 3ns delay to the dclk output. hvocr[1:0] ? free runni ng video mode select bits these two bits together with mu l[7:4] and vrs[7:4] in the pll programming register determine the frequencies of the internal generated free-running si gnals for output to hout, vout, de, and dclk pins, when the sout bit is set in the syn c processor i/o control register. these two bits determine the presca ler of pll reference clock in the cgm module. when hvoc r[1:0]=11, the prescaler is 2; for other values, t he prescaler is 3. reset clears these bits, setting a default horizontal frequency of 31.25khz and a ve rtical frequency of 60hz, a video mode of 640 480. address: $003f bit 7654321bit 0 read: dclkph1 dclkph0 r hvocr1 hvocr0 write: reset: 00 00 = unimplemented r = reserved figure 8-6. h&v sy nc output control register (hvocr) register settings pin outputs video modes hvocr[1:0] mul[7:4] vrs[7:4] hout frequency vout frequency dclk frequency de video mode 00 3 3 31.45khz 59.91hz 24mhz vga 640 480 01 5 3 37.87khz 60.31hz 40mhz svga 800 600 10 8 6 48.37khz 60.31hz 64mhz xga 1024 768 11 9 9 64.32khz 60.00hz 108mhz sxga 1280 1024
clock generator module (cgm) interrupts mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor clock generator module (cgm) 105 8.7 interrupts when the auto bit is set in the pll bandwidth control register (pbwc), the pll can generate a cpu interrupt request ev ery time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupts from the pll. pllf, the interrupt flag in the pctl, becomes set whether interrupts ar e enabled or not. when the auto bit is clear, cpu interrupts from the pll are disabl ed and pllf reads as 0. software should read the lock bit after a pll interrupt request to see if the request was due to an entry into lock or an exit fr om lock. when the pll enters lock, the vco clock cgmv clk, can be se lected as the dclk1 source by setti ng bcs in the pctl. when the pll exits lock, the vco clock frequency is corrupt, and appropriate precautions should be taken. if the application is not fr equency-sensitive, interrupts should be disabled to prevent p ll interrupt service r outines from impeding software performance or from exceeding stack limitations. software can select cgmvclk as t he dclk1 source even if the pll is not locked (lock = 0). therefore, so ftware should make sure the pll is locked before setting the bcs bit. 8.8 low-power modes the wait and stop in structions put the mcu in low-power- consumption standby modes. 8.8.1 wait mode the wait instruction does not affect the cgm. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control r egister (pctl). less power-sensitive applications can disengage the pll without turning it off. applications that require the pll to wake t he mcu from wait mode also can deselect the pll output wit hout turning off the pll.
clock generator module (cgm) technical data mc68hc908ld60 ? rev. 1.1 106 clock generator module (cgm) freescale semiconductor 8.8.2 stop mode when the stop instruction execut es, the sim drives the simoscen signal low, disabling the cgm and holding low all cgm outputs (oscxclk, dclk1, and cgmint). if the stop instruction is execut ed with the vco clock, cgmvclk, driving dclk1, the pll automatically clears the bcs bit in the pll control register (pctl), thereby selecting the cr ystal clock, oscxclk, as the source of dclk1. when th e mcu recovers from stop, the crystal clock drives dclk1 and bcs remains clear. 8.9 cgm during break interrupts the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the sim break flag contro l register (sbfcr) enabl es software to clear status bits during the break state. see section 9. system integration module (sim) . to allow software to clear status bits during a break interrupt, a 1 should be written to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the pllf bit durin g the break state, write a 0 to the bcfe bit. with bcfe at 0 (its def ault state), software can read and wr ite the pll control register during the break state without affecting t he pllf bit.
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 107 technical data ? mc68hc908ld60 section 9. system integration module (sim) 9.1 contents 9.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.3 sim bus clock control and generation . . . . . . . . . . . . . . . . . 111 9.3.1 bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.3.2 clock start-up from po r . . . . . . . . . . . . . . . . . . . . . . . . . . 111 9.3.3 clocks in stop mode and wait mode . . . . . . . . . . . . . . . . . 111 9.4 reset and system initiali zation. . . . . . . . . . . . . . . . . . . . . . . . 112 9.4.1 external pin reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.4.2 active resets from in ternal sources . . . . . . . . . . . . . . . . . 113 9.4.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 9.4.2.2 computer operati ng properly (cop) rese t. . . . . . . . . . 115 9.4.2.3 low-voltage inhibit re set . . . . . . . . . . . . . . . . . . . . . . .115 9.4.2.4 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 9.4.2.5 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . .116 9.5 sim counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9.5.1 sim counter during power-on rese t . . . . . . . . . . . . . . . . 116 9.5.2 sim counter during stop mode re covery . . . . . . . . . . . . . 116 9.5.3 sim counter and reset states. . . . . . . . . . . . . . . . . . . . . . 117 9.6 exception control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 9.6.1 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 9.6.1.1 hardware interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 9.6.1.2 swi instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.6.2 interrupt status regist ers. . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.6.2.1 interrupt stat us register 1 . . . . . . . . . . . . . . . . . . . . . . . 123 9.6.2.2 interrupt stat us register 2 . . . . . . . . . . . . . . . . . . . . . . . 123 9.6.3 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.6.4 break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9.6.5 status flag protection in break mode . . . . . . . . . . . . . . . . 124
system integration module (sim) technical data mc68hc908ld60 ? rev. 1.1 108 system integration module (sim) freescale semiconductor 9.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 9.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 9.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 9.8 sim registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 9.8.1 sim break status register (sbsr) . . . . . . . . . . . . . . . . . . 128 9.8.2 sim reset status register (srsr) . . . . . . . . . . . . . . . . . . 129 9.8.3 sim break flag control register (sbfcr) . . . . . . . . . . . . 130 9.2 introduction this section describes th e system integration mo dule, which supports up to 16 external and/or internal interrupts. t ogether with the cpu, the sim controls all mcu activities. a blo ck diagram of the sim is shown in figure 9-1 . figure 9-2 shows a summary of th e sim i/o registers. the sim is a system state controller that coordi nates cpu and exception timing. the sim is responsible for: bus clock generation and cont rol for cpu and peripherals: ? stop/wait/reset/bre ak entry and recovery ? internal clock control master reset control, includi ng power-on reset (por) and cop timeout interrupt control: ? acknowledge timing ? arbitration control timing ? vector address generation cpu enable/disable timing modular architecture exp andable to 128 interrupt sources
system integration module (sim) introduction mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 109 figure 9-1. sim block diagram stop/wait clock control clock generators por control reset pin control sim reset status register interrupt control and priority decode module stop module wait cpu stop (from cpu) cpu wait (from cpu) simoscen (to oscillator) oscout (from oscillator) internal clocks master reset control reset pin logic lvi (from lvi module) illegal opcode (from cpu) illegal address (from address map decoders) cop (from cop module) interrupt sources cpu interface reset control sim counter cop clock oscxclk (from oscillator) 2 lvi reset
system integration module (sim) technical data mc68hc908ld60 ? rev. 1.1 110 system integration module (sim) freescale semiconductor table 9-1 shows the internal signal na mes used in this section. addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 0 $fe01 sim reset status register (srsr) read: por pin cop ilop ilad r 0 0 write: por:10000 00 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe04 interrupt status register 1 (int1) read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 $fe05 interrupt status register 2 (int2) read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 note: writing a logic 0 clears sbsw. = unimplemented r = reserved figure 9-2. sim i/o register summary table 9-1. signal name conventions signal name description oscxclk buffered version of osc1 from the oscillator oscout the oscxclk frequency divided by two. this signal is again divided by two in the sim to generate the internal bus clocks. (bus clock = oscxclk divided by four) iab internal address bus idb internal data bus porrst signal from the power-on reset module to the sim irst internal reset signal r/w read/write signal
system integration module (sim) sim bus clock control and generation mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 111 9.3 sim bus clock control and generation the bus clock generator provides system clock signal s for the cpu and peripherals on the mcu. the syst em clocks are generated from an incoming clock, oscout, as shown in figure 9-3 . figure 9-3. osc clock signals 9.3.1 bus timing in user mode, the inte rnal bus frequency is t he oscillator frequency (oscxclk) divided by four. 9.3.2 clock start-up from por when the power-on reset module generat es a reset, t he clocks to the cpu and peripherals are inactive an d held in an inactive phase until after the 4096 oscxclk cycle por time out has comple ted. the rst is driven low by the sim du ring this entire period. the ibus clocks start upon completion of the timeout. 9.3.3 clocks in stop mode and wait mode upon exit from stop mode (by an interrupt, brea k, or reset), the sim allows oscxclk to clock the si m counter. the cpu and peripheral clocks do not become active until after the stop del ay timeout. this timeout is selectable as 4096 or 32 oscxclk cycles. (see 9.7.2 stop mode .) simoscen oscxclk from sim 2 oscout osc1 osc2 2 bus clock generators sim sim counter oscillator
system integration module (sim) technical data mc68hc908ld60 ? rev. 1.1 112 system integration module (sim) freescale semiconductor in wait mode, t he cpu clocks are inactive. th e sim also produces two sets of clocks for other modules. refer to the wait mode subsection of each module to see if t he module is active or i nactive in wait mode. some modules can be programmed to be active in wait mode. 9.4 reset and system initialization the mcu has the following reset sources: power-on reset module (por) external reset pin (rst ) computer operating pr operly module (cop) low-voltage inhibit (lvi) illegal opcode illegal address all of these resets produce the vector $fffe?ffff ($fefe?feff in monitor mode) and assert the internal reset signal (irst). irst causes all registers to be returned to thei r default values and all modules to be returned to thei r reset states. an internal reset cl ears the sim counter (see 9.5 sim counter ), but an external reset does not. each of th e resets sets a co rresponding bit in the sim reset status register (srsr) (see 9.8 sim registers ). 9.4.1 external pin reset pulling the asynchronous rst pin low halts all pr ocessing. the pin bit of the sim reset status register (srsr) is set as long as rst is held low for a minimum of 67 os cxclk cycles, assuming th at the por was not the source of the reset (see table 9-2. pin bit set timing) . figure 9-4 shows the relative timing. table 9-2. pin bit set timing reset type number of cycles required to set pin por 4163 (4096 + 64 + 3) all others 67 (64 + 3)
system integration module (sim) reset and system initialization mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 113 figure 9-4. extern al reset timing 9.4.2 active resets from internal sources sim module in hc08 has the capability to drive the rst pin low when internal reset events occur. all internal reset sour ces actively pull the rst pin low for 32 oscxclk cycles to allow resetting of external peripherals. the inte rnal reset signal irst continues to be assert ed for an additi onal 32 cycles (see figure 9- 5. internal reset timing) . an internal reset ca n be caused by an illegal address, illegal opcode, cop timeout, or por (see figure 9-6. sources of internal reset) . note that for por rese ts, the sim cycles through 4096 oscxclk cycles during whic h the sim forces the rst pin low. the internal reset signal then follows the sequence from the falling edge of rst shown in figure 9-5 . the cop reset is asynchro nous to the bus clock. the active reset feature allows the par t to issue a reset to peripherals and other chips within a system built around the mcu. figure 9-5. inter nal reset timing figure 9-6. sources of internal reset rst iab pc vect h vect l oscout irst rst rst pulled low by mcu iab 32 cycles 32 cycles vector high oscxclk illegal address rst illegal opcode rst coprst por internal reset lvi
system integration module (sim) technical data mc68hc908ld60 ? rev. 1.1 114 system integration module (sim) freescale semiconductor 9.4.2.1 power-on reset when power is first applied to the mcu, the power-on reset module (por) generates a pul se to indicate that pow er-on has occurred. the external reset pin (rst ) is held low while the sim counter counts out 4096 oscxclk cycles. sixty-four osc xclk cycles later, the cpu and memories are released from reset to allow the reset vector sequence to occur. at power-on, the foll owing events occur: a por pulse is generated. the internal reset signal is asserted. the sim enables the oscill ator to drive oscxclk. internal clocks to the cpu and m odules are held i nactive for 4096 oscxclk cycles to allow stab ilization of t he oscillator. the rst pin is driven low during th e oscillator stabilization time. the por bit of the sim reset status register (srsr) is set and all other bits in the register are cleared. figure 9-7. por recovery porrst osc1 oscxclk oscout rst iab 4096 cycles 32 cycles 32 cycles $fffe $ffff
system integration module (sim) reset and system initialization mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 115 9.4.2.2 computer operat ing properly (cop) reset an input to the sim is reserved for the cop reset signal. the overflow of the cop counter causes an internal reset and sets the cop bit in the sim reset status register (srsr). the sim actively pulls down the rst pin for all intern al reset sources. to prevent a cop module timeout, wr ite any value to location $ffff. writing to location $ffff clears th e cop counter and bits 12 through 5 of the sim counter. the s im counter output, which o ccurs at least every 2 12 ? 2 4 oscxclk cycles, drives the cop counter. the cop should be serviced as soon as possible out of reset to guarantee the maximum amount of time befor e the first timeout. the cop module is disabled if the rst pin or the irq is held at v tst while the mcu is in monitor m ode. the cop modul e can be disabled only through combinational logic conditioned with the high voltage signal on the rst pin or the irq pin. this prevents the cop from becoming disabled as a result of external noise. during a break state, v tst on the rst pin disables the cop module. 9.4.2.3 low-volt age inhibit reset the low-voltage inhibit circuit perfo rms an internal reset when the v dd voltage falls to the lvi trip voltage v tripf . the external reset pin (rst ) is held low while the sim counter counts out 4096 oscxclk cycles. sixty-four oscxclk cycl es later, the cpu and memories are released from reset to allow the re set vector sequence to occur. 9.4.2.4 illegal opcode reset the sim decodes signals from the cpu to detect illegal instructions. an illegal instruction sets the ilop bi t in the sim reset status register (srsr) and causes a reset. if the stop enable bit, st op, in the confi gure register (config) is logic zero, the sim treats the stop in struction as an illegal opcode and causes an illegal opcode reset. the sim actively pulls down the rst pin for all internal reset sources.
system integration module (sim) technical data mc68hc908ld60 ? rev. 1.1 116 system integration module (sim) freescale semiconductor 9.4.2.5 illegal address reset an opcode fetch from an unm apped address genera tes an illegal address reset. the sim ve rifies that t he cpu is fetching an opcode prior to asserting the ilad bit in the si m reset status register (srsr) and resetting the mcu. a data fetch from an unmapped address does not generate a reset. the sim acti vely pulls down the rst pin for all internal reset sources. 9.5 sim counter the sim counter is used by the pow er-on reset module (por) and in stop mode recovery to allow the os cillator time to stabilize before enabling the internal bus (i bus) clocks. the sim c ounter also serves as a prescaler for the computer operati ng properly module (cop). the sim counter overflow supplies the cl ock for the cop module. the sim counter is 12 bits long and is clo cked by the falling edge of oscxclk. 9.5.1 sim counter during power-on reset the power-on reset module (por) dete cts power appli ed to the mcu. at power-on, the por ci rcuit asserts the signal porrst. once the sim is initialized, it enables the oscillator to drive the bus clock state machine. 9.5.2 sim counter during stop mode recovery the sim counter also is used for stop mode recovery. the stop instruction clears the sim counter. af ter an interrupt, brea k, or reset, the sim senses the state of the short stop recovery bit, ssrec, in the configure register (con fig). if the ssrec bit is a logic one, then the stop recovery is reduced from the normal delay of 4096 oscxclk cycles down to 32 oscxclk cycles. thi s is ideal for applications using canned oscillators that do not require long st art-up times from stop mode. external crystal applications should use the full stop recovery time, that is, wi th ssrec cleared.
system integration module (sim) exception control mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 117 9.5.3 sim counter and reset states external reset has no ef fect on the sim counter (see 9.7.2 stop mode ). the sim counter is free-running after all reset states ( see 9.4.2 active resets from internal sources for counter control and internal reset recovery sequences). 9.6 exception control normally, sequential program exec ution can be c hanged in three different ways: interrupts ? maskable hardware cpu interrupts ? non-maskable software interrupt instruction (swi) reset break interrupts
system integration module (sim) technical data mc68hc908ld60 ? rev. 1.1 118 system integration module (sim) freescale semiconductor 9.6.1 interrupts an interrupt temporarily changes th e sequence of program execution to respond to a parti cular event. figure 9-10 flow charts the handling of system interrupts. interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which ve ctor to fetch. once an interrupt is latched by the sim, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serv iced (or the i bit is cleared). at the beginning of an interrupt, the cpu sa ves the cpu register contents on the sta ck and sets the interrupt ma sk (i bit) to prevent additional interrupts. at the end of an interrupt , the rti instruction recovers the cpu regist er contents from the stack so that normal processing can resume. figure 9-8 shows interrupt entry timing. figure 9-9 shows interrupt recovery timing. figure 9-8 . interrupt entry figure 9-9. interrupt recovery module idb r/w interrupt dummy sp sp ? 1 sp ? 2 sp ? 3 sp ? 4 vect h vect l start addr iab dummy pc ? 1[7:0] pc ? 1[15:8] x a ccr v data h v data l opcode i bit module idb r/w interrupt sp ? 4 sp ? 3 sp ? 2 sp ? 1 sp pc pc + 1 iab ccr a x pc ? 1[7:0] pc ? 1[15:8] opcode operand i bit
system integration module (sim) exception control mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 119 figure 9-10. interrupt processing no no no yes no no yes no yes yes (as many interrupts as exist on chip) i bit set? from reset break interrupt? i bit set? irq interrupt? ddc12ab interrupt? swi instruction? rti instruction? fetch next instruction. unstack cpu registers. stack cpu registers. set i bit. load pc with interrupt vector. execute instruction. yes yes
system integration module (sim) technical data mc68hc908ld60 ? rev. 1.1 120 system integration module (sim) freescale semiconductor interrupts are latched, and arbitration is performed in the sim at the start of interrupt processing. the arbitration result is a constant that the cpu uses to determine which ve ctor to fetch. once an interrupt is latched by the sim, no other interrup t may take precedence, regardless of priority, until the latched interrupt is servic ed (or the i bit is cleared). (see figure 9-10. interrupt processing .) 9.6.1.1 hardware interrupts a hardware interrupt does not stop the current in struction. processing of a hardware interrupt begins after completion of t he current instruction. when the current instruction is complete, the sim checks all pending hardware interrupts. if interrupts ar e not masked (i bit clear in the condition code register), and if the corres ponding interrupt enable bit is set, the sim proceeds with interrup t processing; other wise, the next instruction is fetched and executed. if more than one interrupt is pending at th e end of an instruction execution, the highest priority interrupt is serviced first. figure 9-11 demonstrates what hap pens when two interrupts are pending. if an interrupt is pending upon exit from the original inte rrupt service routine, the pending interrupt is serviced before the lda in struction is executed. figure 9-11 . interrupt recognition example cli lda int1 pulh rti int2 background routine #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine
system integration module (sim) exception control mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 121 the lda opcode is pre- fetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti pre-fetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during in terrupt entry. if the in terrupt service routine modifies the h register or uses the indexed addressing mode, software should save the h register and then restore it prio r to exiting the routine. 9.6.1.2 swi instruction the swi instruction is a non-maskable instruct ion that causes an interrupt regardless of the state of the interrupt mask (i bit) in the condition code register. note: a software interrupt pushes pc onto the stack. a software interrupt does not push pc ? 1, as a hardware interrupt does. 9.6.2 interrupt status registers the flags in the interrupt status re gisters identify maskable interrupt sources. table 9-3 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging.
system integration module (sim) technical data mc68hc908ld60 ? rev. 1.1 122 system integration module (sim) freescale semiconductor table 9-3. interrupt sources source flag mask (1) int register flag priority (2) vector address reset none none none 0 $fffe?$ffff swi instruction none none none 0 $fffc?$fffd irq pin irqf imask if1 1 $fffa?$fffb reserved ? ? if2 2 $fff8?$fff9 reserved ? ? if3 3 $fff6?$fff7 reserved ? ? if4 3 $fff4?$fff5 ddc12ab alif dien if5 5 $fff2?$fff3 nakif rxif txif sclif sclien tim channel 0 ch0f ch0ie if6 6 $fff0?$fff1 tim channel 1 ch1f ch1ie if7 7 $ffee?$ffef tim overflow tof toie if8 8 $ffec?$ffed sync processor vsif vsie if9 9 $ffea?$ffeb lvsif lvsie multi-master iic mmalif mmien if10 10 $ffe8?ffe9 mmnakif mmrxif mmtxif reserved ? ? if11 11 $ffe6?$ffe7 adc conversion complete coco aien if12 12 $ffe4?$ffe5 keyboard interrupt keyf kbi e7?kbie0 if13 13 $ffe2?$ffe3 cgm pll pllf pllie if14 14 $ffe0?$ffe1 notes : 1. the i bit in the condition code register is a global mask for all interrupt sources except the swi instruction. 2. highest priority = 0.
system integration module (sim) exception control mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 123 9.6.2.1 interrupt status register 1 if6?if1 ? interrupt flags 6?1 these flags indicate the presence of interrupt r equests from the sources shown in table 9-3 . 1 = interrupt request present 0 = no interrupt request present bit 1and bit 0 ? always read 0 9.6.2.2 interrupt status register 2 if14?if7 ? interrupt flags 6?1 these flags indicate the presence of interrupt r equests from the sources shown in table 9-3 . 1 = interrupt request present 0 = no interrupt request present address: $fe04 bit 7654321bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write:rrrrrrrr reset:00000000 r= reserved figure 9-12. interrupt st atus register 1 (int1) address: $fe05 bit 7654321bit 0 read: if14 if13 if12 if11 if10 if9 if8 if7 write:rrrrrrrr reset:00000000 r= reserved figure 9-13. interrupt st atus register 2 (int2)
system integration module (sim) technical data mc68hc908ld60 ? rev. 1.1 124 system integration module (sim) freescale semiconductor 9.6.3 reset all reset sources always have equal and highest pr iority and cannot be arbitrated. 9.6.4 break interrupts the break module can st op normal program flow at a software- programmable break point by asserti ng its break interrupt output (see section 21. break module (brk) ). the sim puts t he cpu into the break state by forcing it to the swi vector loca tion. refer to the break interrupt subsection of each module to see how each module is affected by the break state. 9.6.5 status flag protection in break mode the sim controls whether status fl ags contained in ot her modules can be cleared during break m ode. the user can sele ct whether flags are protected from being clea red by properly initiali zing the break clear flag enable bit (bcfe) in t he sim break flag contro l register (sbfcr). protecting flags in break mode ensures that set flags will not be cleared while in break mode. this protection allows registers to be freely read and written during break mode without losing st atus flag information. setting the bcfe bit e nables the clearing mechani sms. once cleared in break mode, a flag remains cleared even when break mode is exited. status flags with a two-step cleari ng mechanism ? for example, a read of one register followed by the read or write of another ? are protected, even when the first step is accomplished prior to entering break mode. upon leaving break mode, execution of the second step will clear the flag as normal.
system integration module (sim) low-power modes mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 125 9.7 low-power modes executing the wait or stop instruction puts t he mcu in a low-power- consumption mode for st andby situations. the s im holds the cpu in a non-clocked state. the operation of eac h of these mode s is described below. both stop and wait clear the interrupt mask (i) in the condition code register, allowing interrupts to occur. 9.7.1 wait mode in wait mode, t he cpu clocks are inactive while the peripheral clocks continue to run. figure 9-14 shows the timing fo r wait mode entry. a module that is active during wa it mode can wake up the cpu with an interrupt if the interrupt is enabled . stacking for the interrupt begins one cycle after the wait instruction duri ng which the interr upt occurred. in wait mode, the cpu clocks are i nactive. refer to the wait mode subsection of each module to see if th e module is active or inactive in wait mode. some modules can be programmed to be active in wait mode. wait mode can also be exited by a reset or break. a break interrupt during wait mode sets the sim break stop/wait bit, sbsw, in the sim break status register (sbsr). if the cop disable bit, copd, in configuration register (config) is logic ze ro, then the computer operating properly module (cop) is enabled and remains active in wait mode. figure 9-14. wait mode entry timing figure 9-15 and figure 9-16 show the timing for wait recovery. wait addr + 1 same same iab idb previous data next opcode same wait addr same r/w note: previous data can be operand data or th e wait opcode, depending on the last instruction.
system integration module (sim) technical data mc68hc908ld60 ? rev. 1.1 126 system integration module (sim) freescale semiconductor figure 9-15. wait recovery from interrupt or break figure 9-16. wait recover y from internal reset 9.7.2 stop mode in stop mode, the sim counter is reset and the system clocks are disabled. an interrupt request from a module can cause an exit from stop mode. stacking for inte rrupts begins after the selected stop recovery time has elapsed. reset or break al so causes an exit from stop mode. the sim disables the oscillator si gnals (oscout and oscxclk) in stop mode, stopping the cpu and peripherals. stop recovery time is selectable using the ssrec bit in configuration register (config). if ssrec is set, stop recovery is reduced from the nor mal delay of 4096 oscxclk cycles down to 32. this is ideal for applications using canned oscillators that do not require lo ng start-up times from stop mode. note: external crystal applicati ons should use the full stop recovery time by clearing the ssrec bit. $6e0c $6e0b $00ff $00fe $00fd $00fc $a6 $a6 $01 $0b $6e $a6 iab idb exitstopwait note: exitstopwait = rst pin or cpu interrupt or break interrupt iab idb rst $a6 $a6 $6e0b rst vct h rst vct l $a6 oscxclk 32 cycles 32 cycles
system integration module (sim) low-power modes mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 127 a break interrupt during stop mode sets the si m break stop/wait bit (sbsw) in the sim break st atus register (sbsr). the sim counter is held in reset from the execution of the stop instruction until th e beginning of stop recovery. it is then used to time the recovery period. figure 9-17 shows stop mode entry timing. figure 9-17. stop mode entry timing figure 9-18. stop mode recovery from interrupt or break stop addr + 1 same same iab idb previous data next opcode same stop addr same r/w cpustop note: previous data can be operand data or t he stop opcode, depending on the last instruction. oscxclk int/break iab stop + 2 stop + 2 sp sp ? 1 sp ? 2 sp ? 3 stop +1 stop recovery period
system integration module (sim) technical data mc68hc908ld60 ? rev. 1.1 128 system integration module (sim) freescale semiconductor 9.8 sim registers the sim has three memo ry mapped registers. table 9-4 shows the mapping of thes e registers. 9.8.1 sim break status register (sbsr) the sim break status register contains a flag to indica te that a break caused an exit from st op or wait mode. sbsw ? sim break stop/wait bit this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. re set clears sbsw. 1 = stop mode or wa it mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break interrupt routine. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example. table 9-4. sim registers summary address register access mode $fe00 sbsr user $fe01 srsr user $fe03 sbfcr user address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note reset: 0 note: writing a logic 0 clears sbsw. r= reserved figure 9-19. sim break stat us register (sbsr)
system integration module (sim) sim registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor system integration module (sim) 129 9.8.2 sim reset status register (srsr) this register contains six flags that show the sour ce of the last reset. clear the sim reset status register by reading it. a power-on reset sets the por bit and clear s all other bits in the register. por ? power-on reset bit 1 = last reset caused by por circuit 0 = read of srsr pin ? external reset bit 1 = last reset caused by external reset pin (rst ) 0 = por or read of srsr ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register. address: $fe01 bit 7654321bit 0 read: por pin cop ilop ilad r 0 0 write: por:10000 00 = unimplemented r = reserved figure 9-20. sim reset status register (srsr)
system integration module (sim) technical data mc68hc908ld60 ? rev. 1.1 130 system integration module (sim) freescale semiconductor cop ? computer operati ng properly reset bit 1 = last reset caused by cop counter 0 = por or read of srsr ilop ? illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of srsr ilad ? illegal address rese t bit (opcode fetches only) 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of srsr 9.8.3 sim break flag control register (sbfcr) the sim break flag control r egister contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to cl ear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r= reserved figure 9-21. sim break flag c ontrol register (sbfcr)
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 131 technical data ? mc68hc908ld60 section 10. monitor rom (mon) 10.1 contents 10.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 10.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 10.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 10.4.1 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 10.4.2 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 10.4.3 echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.4.4 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 10.4.5 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 10.4.6 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 10.2 introduction this section describes the monitor rom (mon) and the monitor mode entry methods. the monitor rom allows complete testing of the mcu through a single-wir e interface with a host computer. monitor mode entry can be achieved without use of the higher test voltage, v tst , as long as vector addresses $fffe and $ffff are blank, thus reducing the hardware requirements fo r in-circuit programming.
monitor rom (mon) technical data mc68hc908ld60 ? rev. 1.1 132 monitor rom (mon) freescale semiconductor 10.3 features features of the mo nitor rom include: normal user-mode pin functionality one pin dedicated to serial co mmunication between monitor rom and host computer standard mark/space non-return -to-zero (nrz) communication with host computer execution of code in ram or flash flash memory security feature 1 flash memory progr amming interface 1024 bytes monitor rom code size ($fa00 to $fdff) monitor mode entry wi thout high voltage, v tst , if reset vector is blank ($fffe and $ffff contain $ff) standard monitor mode entry if high voltage, v tst , is applied to irq 10.4 functional description the monitor rom receives and exec utes commands from a host computer. figure 10-1 shows a sample circuit used to enter monitor mode and communicate with a host computer via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute c ode downloaded into ram by a host computer while most mcu pins reta in normal operating mode functions. all communication between the host computer and t he mcu is through the pta0 pin. a level-shifting and multiplexing interface is required between pta0 and the host computer. pta0 is used in a wired-or configuration and require s a pull-up resistor. 1. no security feature is absolutely secure. howe ver, freescale?s strategy is to make reading or copying the flash difficult for unauthorized users.
monitor rom (mon) functional description mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 133 figure 10-1. moni tor mode circuit + + + + 10 m ? x1 v dd mc145407 mc74lcx125 68hc908ld60 rst irq osc1 osc2 v ss1 v dd 1 pta0 v dd 10 k ? 0.1 f 6 5 2 4 3 1 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 20 pf 20 pf 10 f 10 f 10 f 10 f 1 2 4 7 14 3 0.1 f 9.8304 mhz 10 k ? ptc3 v dd 10 k ? b a (see notes) 5 6 ptc0 ptc1 v dd 10 k ? v ss2 v dd 2 v ssa v dd a 0.1 f v dd (pin 6) (pin 7) ptd4 ptd5 pta7 v tst 10 ? d c (see notes) sw2 sw1 notes: 1. sw2: position c ? for monitor mode entry when irq = v tst : sw1: position a ? bus clock = oscxclk 4 sw1: position b ? bus clock = oscxclk 2 2. sw2: position d ? for monitor mode entry when reset vector is blank ($fffe and $ffff = $ff): bus clock = oscxclk 4; ptc0, ptc1, and ptc3 voltages are not required. 3. see table 22-4 for irq voltage level requirements.
monitor rom (mon) technical data mc68hc908ld60 ? rev. 1.1 134 monitor rom (mon) freescale semiconductor 10.4.1 entering monitor mode table 10-1 shows the pin conditions fo r entering monitor mode. as specified in the table, monitor mode may be entered after a power-on reset (por) and will allow communi cation at 9600 baud provided one of the following sets of conditions is met: 1. if monitor entry is by high voltage on irq (irq = v tst ) ? the external clock is 4. 9152 mhz with pt c3 low or 9.8304 mhz with ptc3 high 2. if monitor entry is by blank reset vect or ($fffe and $ffff both contain $ff; erased state): ? the external clock is 9.8304 mhz note: holding the ptc3 pin low when ente ring monitor mode by a high voltage causes a bypass of a divide-by-two stage at the oscillator. the oscout frequency is equal to the oscxclk frequency, and the osc1 input directly generates internal bus clocks. in this case, the osc1 signal must have a 50% duty cycle at maximum bus frequency. note: if the reset vector is blank and moni tor mode is entered, the chip will see an additional reset cycle after the init ial por reset. once the part has been programmed, the traditi onal method of applyi ng a high voltage, v tst , to irq must be used to enter monitor mode. enter monitor mode with the pin configuration shown in table 10-1 after a reset. the rising edge of reset la tches monitor mode. once monitor mode is latched, the values on the specif ied pins can change. once out of reset, t he mcu monitor mode firmwa re then sends a break signal (10 consecutive logi c zeros) to the host co mputer, indicating that it is ready to receive a command. the break signal also provides a timing reference to allow t he host to determine t he necessary baud rate.
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 135 monitor rom (mon) functional description table 10-1. monitor mode si gnal requirement s and options irq rst address $fffe/ $ffff ptc3 ptc1 ptc0 pta7 (1) pin 6 pin 7 ptd4 ptd5 external clock (2) bus frequency cop baud rate comment xgndx xxxx x x 0disabled0no operation until reset goes high. v tst v dd or v tst x 0010 0 4. 9152 mhz 2.4576 mhz disabled 9600 enters monitor mode. ptc0, ptc1, and ptc3 voltages only required if irq = v tst ; ptc3 determines frequency divider. exit monitor mode by por or by rst low then high v tst v dd or v tst x 1010 0 9. 8304 mhz 2.4576 mhz disabled 9600 enters monitor mode. ptc0, ptc1, and ptc3 voltages only required if irq = v tst ; ptc3 determines frequency divider. exit monitor mode by por or by rst low then high v dd or gnd v dd blank "$ffff" x x x 0 0 9.8304 mhz 2.4576 mhz disabled 9600 enters monitor mode. external frequency always divided by 4. exit monitor mode by por only. v dd or gnd v dd not blankxxxx x x ?enabled?enters user mode. notes : 1. pta7 = 0 if serial communication; pta7 = 1 if parallel communication 2. external clock is derived by a 4.9152/9 .8304 mhz crystal or off-chip oscillator
monitor rom (mon) technical data mc68hc908ld60 ? rev. 1.1 136 monitor rom (mon) freescale semiconductor monitor mode uses differ ent vectors for reset and swi. the alternate vectors are in the $fe page in stead of the $ff page and allow code execution from the internal monito r firmware instead of user code. when the host computer has comple ted downloading code into the mcu ram, this code can be executed by driving pta0 low while asserting rst low and then high. the internal monitor rom fi rmware will interpret the low on pta0 as an i ndication to jump to ra m, and execution control will then continue from ram. execution of an swi from the downloaded code will return program control to the internal monitor rom firmware. alternatively, the host can send a run command, whic h executes an rti, and this can be used to send control to the addr ess on the stack pointer. the cop module is disabled in monitor mode as long as v tst is applied to the irq or the rst pin. (see section 9. system integration module (sim) for more information on modes of operation.) table 10-2 is a summary of the differ ences between user mode and monitor mode. 10.4.2 data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. (see figure 10-2 and figure 10-3 .) table 10-2. mode differences modes functions cop reset vector high reset vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd monitor disabled (1) notes : 1. if the high voltage (v tst ) is removed from the irq pin, the sim asserts its cop enable output. the cop is an option enabled or disa bled by the copd bit in the configuration register. $fefe $feff $fefc $fefd
monitor rom (mon) functional description mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 137 figure 10-2. moni tor data format figure 10-3. sample monitor waveforms the data transmit and receive rate can be anywhere fr om 4800 baud to 28.8 kbaud. transmit and receive baud rates must be identical. 10.4.3 echoing as shown in figure 10-4 , the monitor rom immediately echoes each received byte back to the pt a0 pin for error checking. figure 10-4. read transaction any result of a command appears after the ec ho of the last byte of the command. 10.4.4 break signal a start bit followed by ni ne low bits is a break signal (see figure 10-5). when the monitor receives a break sign al, it drives the pta0 pin high for the duration of tw o bits before echoi ng the break signal. bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 bit 5 start bit bit 0 bit 1 next stop bit start bit bit 2 bit 3 bit 4 bit 6 bit 7 start bit bit 0 bit 1 stop bit bit 2 $a5 break bit 3 bit 4 bit 5 bit 6 bit 7 addr. high read read addr. high addr. low addr. low data echo sent to monitor result
monitor rom (mon) technical data mc68hc908ld60 ? rev. 1.1 138 monitor rom (mon) freescale semiconductor figure 10-5. break transaction 10.4.5 commands the monitor rom uses t he following commands: read (read memory) write (write memory) iread (indexed read) iwrite (indexed write) readsp (read stack pointer) run (run user program) 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 missing stop bit two-stop-bit delay before zero echo table 10-3. read (r ead memory) command description read byte from memory operand specifies 2-byte address in high byte:low byte order data returned returns contents of specified address opcode $4a command sequence read read echo sent to monitor address high address high address low data return address low
monitor rom (mon) functional description mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 139 table 10-4. write (write memory) command description write byte to memory operand specifics 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence table 10-5. iread (i ndexed read) command description read next 2 bytes in memory from last address accessed operand specifies 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence write write echo semt to monitor address high address high address low address low data data iread iread echo sent to monitor data return data
monitor rom (mon) technical data mc68hc908ld60 ? rev. 1.1 140 monitor rom (mon) freescale semiconductor a sequence of iread or iwrite commands can sequentially access a block of memory over the full 64k-byte memory map. table 10-6. iwrite (i ndexed write) command description write to last address accessed + 1 operand specifies single data byte data returned none opcode $19 command sequence table 10-7. read sp (read stack pointer) command description reads stack pointer operand none data returned returns stack pointer in high byte:low byte order opcode $0c command sequence iwrite iwrite echo sent to monitor data data readsp readsp echo sent to monitor sp return sp high low
monitor rom (mon) functional description mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor monitor rom (mon) 141 10.4.6 baud rate the communication baud rate is cont rolled by crystal frequency and the state of the ptc3 pin upon entry into monitor mode. when ptc3 is high, the divide by ratio is 1024. if the ptc3 pin is at logic zero upon entry into monitor mode, the divi de by ratio is 512. table 10-8. run (run u ser program) command description executes rti instruction operand none data returned none opcode $28 command sequence run run echo sent to monitor table 10-9. monitor baud rate selection crystal frequency ptc3 pin baud rate 4.9152 mhz 0 9600 bps 9.8304 mhz 1 9600 bps
monitor rom (mon) technical data mc68hc908ld60 ? rev. 1.1 142 monitor rom (mon) freescale semiconductor
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 143 technical data ? mc68hc908ld60 section 11. timer interface module (tim) 11.1 contents 11.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.4 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 11.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 11.5.1 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.5.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.5.3 output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 11.5.3.1 unbuffered output compare . . . . . . . . . . . . . . . . . . . . . 148 11.5.3.2 buffered output com pare . . . . . . . . . . . . . . . . . . . . . . .149 11.5.4 pulse width modulatio n (pwm) . . . . . . . . . . . . . . . . . . . . . 149 11.5.4.1 unbuffered pwm sig nal generation . . . . . . . . . . . . . . . 150 11.5.4.2 buffered pwm signal generation . . . . . . . . . . . . . . . . . 151 11.5.4.3 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 11.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 11.7 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 11.7.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 11.7.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 11.8 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 154 11.9 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 11.10 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 11.10.1 tim status and control register (tsc) . . . . . . . . . . . . . . . 155 11.10.2 tim counter regist ers (tcnth:tcntl) . . . . . . . . . . . . . . 157 11.10.3 tim counter modul o registers (tmodh:tm odl) . . . . . . 158 11.10.4 tim channel status and co ntrol registers (tsc0:tsc1) . 159 11.10.5 tim channel registers (tch0h /l:tch1h/l) . . . . . . . . . . 162
timer interface module (tim) technical data mc68hc908ld60 ? rev. 1.1 144 timer interface module (tim) freescale semiconductor 11.2 introduction this section describes the timer inte rface module (tim2, version b). the tim is a two-channel time r that provides a timi ng reference with input capture, output compare, and pul se-width-modulation functions. figure 11-1 is a block diagram of the tim. 11.3 features features of the tim include the following: two input capture/ou tput compare channels ? rising-edge, falling-edge, or any-edge input capture trigger ? set, clear, or toggle output compare action buffered and unbuffered pulse width modulation (pwm) signal generation programmable tim clock input ? seven-frequency internal bus clock prescaler selection free-running or modul o up-count operation toggle any channel pin on overflow tim counter stop and reset bits modular architecture expandable to eight channels note: tch1 (timer channel 1) is not bonded to an external pin on this mcu. therefore, any references to the ti mer tch1 pin in the following text should be interpreted as not available ? but the inter nal status and control registers ar e still available. 11.4 pin name conventions the tim shares the tch0 pin with the sync processor clamp output. table 11-1. pin name conventions tim generic pin name: tch0 full tim pin name: clamp/tch0 pin selected for tch0 by: els0b:els0a
timer interface module (tim) functional description mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 145 11.5 functional description figure 11-1 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides the timing reference for the input capture and output co mpare functions. the tim counter modulo registers, tmodh:tmodl, contro l the modulo value of the tim counter. software can read th e tim counter value at any time without affecting the counting sequence. the two tim channels are program mable independently as input capture or output compare channels. figure 11-1. tim block diagram prescaler prescaler select 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a tof toie 16-bit comparator 16-bit latch tch1h:tch1l channel 0 channel 1 tmodh:tmodl trst tstop tov0 ch0ie ch0f els1b els1a tov1 ch1ie ch1max ch1f ch0max ms0b 16-bit counter internal bus ms1a internal bus clock tch1 tch0 interrupt logic port logic interrupt logic interrupt logic port logic (not available)
timer interface module (tim) technical data mc68hc908ld60 ? rev. 1.1 146 timer interface module (tim) freescale semiconductor addr.register name bit 7654321bit 0 $000a tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 $000c tim counter register high (tcnth) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 $000d tim counter register low (tcntl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 $000e tim counter modulo register high (tmodh) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 $000f tim counter modulo register low (tmodl) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 $0010 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 $0011 tim channel 0 register high (tch0h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0012 tim channel 0 register low (tch0l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset $0013 tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000
timer interface module (tim) functional description mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 147 11.5.1 tim counter prescaler the tim clock source can be one of the seven presca ler outputs. the prescaler generates seven clock rate s from the internal bus clock. the prescaler select bits, ps[2:0], in t he tim status and control register (tsc) select the tim clock source. 11.5.2 input capture with the input capture function, the tim can capture the time at which an external event occurs. when an acti ve edge occurs on the pin of an input capture channel, the tim latches the cont ents of the tim counter into the tim channel registers, tc hxh:tchxl. the polarity of the active edge is programmable. input captures can generate tim cpu interrupt requests. 11.5.3 output compare with the output compare function, the tim can gener ate a periodic pulse with a programmable polarity, duration, and fr equency. when the counter reaches the value in the r egisters of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests. $0014 tim channel 1 register high (tch1h) read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset $0015 tim channel 1 register low (tch1l) read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset = unimplemented addr.register name bit 7654321bit 0
timer interface module (tim) technical data mc68hc908ld60 ? rev. 1.1 148 timer interface module (tim) freescale semiconductor 11.5.3.1 unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in 11.5.3 output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel regist ers to change an output compare value could cause incorrect operati on for up to two counter overflow periods. for exampl e, writing a new value before the counter reaches the old value but after the c ounter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt rout ine to write a new, smaller output compare value may caus e the compare to be missed. the tim may pass the new value befor e it is written. use the following methods to synch ronize unbuffered changes in the output compare va lue on channel x: when changing to a smaller va lue, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse . the interrupt routine has until the end of the counter overflow period to write the new value. when changing to a larger out put compare value, enable channel x tim overflow interrupts and write the ne w value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter ov erflow period. writing a larger value in an output co mpare interrupt routin e (at the end of the current pulse) could c ause two output compar es to occur in the same counter overflow period.
timer interface module (tim) functional description mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 149 11.5.3.2 buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of the lin ked pair alternatel y control the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the output comp are value in the tim channel 0 registers initially controls the output on the tch0 pin. writing to the tim channel 1 registers enabl es the tim channel 1 registers to synchronously control t he output after the tim overflows. at each subsequent overflow, the tim channel regi sters (0 or 1) that control the output are the ones writte n to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. note: in buffered output compare operati on, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares. 11.5.4 pulse width modulation (pwm) by using the toggle-on-overflow f eature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determi nes the period of th e pwm signal. the channel pin toggles when the counter reaches the value in the tim counter modulo registers. the time between ov erflows is the period of the pwm signal. as figure 11-2 shows, the output compar e value in the tim channel registers determines t he pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on outpu t compare if the state of the pwm pulse is logic one. program the tim to set the pin if the state of the pwm pulse is logic zero.
timer interface module (tim) technical data mc68hc908ld60 ? rev. 1.1 150 timer interface module (tim) freescale semiconductor figure 11-2. pwm peri od and pulse width the value in the tim counter modu lo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is va riable in 256 in crements. writing $00ff (255) to the ti m counter modulo regi sters produces a pwm period of 256 times the in ternal bus clock period if the prescaler select value is 000 (see 11.10.1 tim status and control register (tsc) ). the value in the tim chan nel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm sign al is variable in 256 increments. writing $008 0 (128) to the tim c hannel registers produces a duty cycle of 128 /256 or 50%. 11.5.4.1 unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in 11.5.4 pulse width modulation (pwm) . the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currentl y in the tim channel registers. an unsynchronized write to the ti m channel registers to change a pulse width value could cause incorrect oper ation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim overflow inte rrupt routine to write a new, smaller pulse width value may caus e the compare to be missed. the tim may pass the new value before it is written. tchx period pulse width overflow overflow overflow output compare output compare output compare
timer interface module (tim) functional description mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 151 use the following methods to synch ronize unbuffered changes in the pwm pulse width on channel x: when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pu lse. the interrupt routi ne has until the end of the pwm period to write the new value. when changing to a longer pulse width, enable channel x tim overflow interrupts a nd write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current pwm period. writin g a larger value in an output compare interrupt routine (at t he end of the curr ent pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare also can cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 11.5.4.2 buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel re gisters of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writ ing to the tim channel 1 registers enables the ti m channel 1 registers to synchronously control the pulse width at t he beginning of the nex t pwm period. at each subsequent overflow, the tim channel regi sters (0 or 1) that control the pulse width are the ones written to last. tsc0 c ontrols and monitors the buffered pwm functi on, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin.
timer interface module (tim) technical data mc68hc908ld60 ? rev. 1.1 152 timer interface module (tim) freescale semiconductor note: in buffered pwm signal gener ation, do not write new pulse width values to the currently active channel registers. writi ng to the acti ve channel registers is the same as gen erating unbuffe red pwm signals. 11.5.4.3 pwm initialization to ensure correct operation when gen erating unbuffered or buffered pwm signals, use the follow ing initializat ion procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by se tting the tim stop bit, tstop. b. reset the tim counter by sett ing the tim reset bit, trst. 2. in the tim counter modulo regi sters (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (t chxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered outp ut compare or pwm signals) or 1:0 (for buffered outp ut compare or pwm si gnals) to the mode select bits, msxb:m sxa. (see table 11-3.) b. write 1 to the toggle- on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level se lect bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. (see table 11-3 .) note: in pwm signal generation , do not program the pw m channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self- correct in the event of software error or noise. toggling on output compare can also cause incorr ect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control regist er (tsc), clear t he tim stop bit, tstop.
timer interface module (tim) interrupts mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 153 setting ms0b links chann els 0 and 1 and configur es them for buffered pwm operation. the tim channel 0 r egisters (tch0h:tch0l) initially control the buffered pwm output. tim status contro l register 0 (tscr0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. clearing the toggle-on-ove rflow bit, tovx, inhibi ts output toggles on tim overflows. subsequent outpu t compares try to forc e the output to a state it is already in and have no effect . the result is a 0% duty cycle output. setting the channel x maximum dut y cycle bit (chxm ax) and clearing the tovx bit generates a 100% duty cycle output. see 11.10.4 tim channel status and control register s (tsc0:tsc1) . 11.6 interrupts the following tim sources can generate interrupt requests: tim overflow flag (tof) ? th e tof bit is set when the tim counter value rolls over to $0000 after matching t he value in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim stat us and control register. tim channel flags ( ch1f:ch0f) ? the chxf bi t is set when an input capture or output compar e occurs on channel x. channel x tim cpu interrupt requests ar e controlled by the channel x interrupt enable bit, chxie. c hannel x tim cpu interrupt requests are enabled when chxie=1. chxf and chxie ar e in the tim channel x status and control register. 11.7 low-power modes the wait and stop in structions puts the mcu in low-power- consumption standby modes. 11.7.1 wait mode the tim remains active after the executi on of a wait instru ction. in wait mode the tima register s are not accessible by the cpu. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode.
timer interface module (tim) technical data mc68hc908ld60 ? rev. 1.1 154 timer interface module (tim) freescale semiconductor if tim functions are not required during wait mode, reduce power consumption by stopping the tim befor e executing the wait instruction. 11.7.2 stop mode the tim is inactive after the executi on of a stop instru ction. the stop instruction does no t affect register conditions or the state of the tim counter. tim operation resumes when the mcu ex it stop mode after an external interrupt. 11.8 tim during break interrupts a break interrupt st ops the tim counter. the system integration module (sim) c ontrols whether status bits in other modules can be cleared during th e break state. the bcfe bit in the break flag control regi ster (bfcr) enables software to clear status bits during the break state. (see 21.6.4 sim break flag control register .) to allow software to clear status bi ts during a break interrupt, write a logic one to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits dur ing the break state, writ e a logic zero to the bcfe bit. with bcfe at logic zero (its default state), software can read and write i/o registers during the br eak state without affecting status bits. some status bits have a two- step read/write cleari ng procedure. if software does the first step on such a bit before the brea k, the bit cannot change during the break stat e as long as bcfe is at logic zero. after the break, doing the second step clears the status bit. 11.9 i/o signals the tim channel i/o pin is clamp/ tch0. the pin is shared with sync processor clamp output signal. tch0 pin is programmable independently as an input capture pin or an output compare pin. it also can be configur ed as a buffered output compare or buffered pwm pin.
timer interface module (tim) i/o registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 155 11.10 i/o registers the following i/o registers control and monitor operation of the tim: tim status and control register (tsc) tim counter registers (tcnth:tcntl) tim counter modulo registers (tmodh:tmodl) tim channel status and con trol registers (tsc0 and tsc1) tim channel registers (tch 0h:tch0l and tch1h:tch1l) 11.10.1 tim status and control register (tsc) the tim status and control r egister does the following: enables tim overflow interrupts flags tim overflows stops the tim counter resets the tim counter prescales the tim counter clock tof ? tim overflow flag bit this read/write flag is set when the tim counter resets to $0000 after reaching the modulo va lue programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and t hen writing a logic zero to tof. if another tim address: $000a bit 7654321bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset:00100000 = unimplemented figure 11-3. tim st atus and control register (tsc)
timer interface module (tim) technical data mc68hc908ld60 ? rev. 1.1 156 timer interface module (tim) freescale semiconductor overflow occurs before the clear ing sequence is complete, then writing logic zero to tof has no effect. ther efore, a tof interrupt request cannot be lost du e to inadvertent clea ring of tof. reset clears the tof bit. writing a l ogic one to tof has no effect. 1 = tim counter has reached modulo value 0 = tim counter has not reached modulo value toie ? tim overflow interrupt enable bit this read/write bi t enables tim overflow in terrupts when the tof bit becomes set. reset cl ears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled tstop ? tim stop bit this read/write bit stop s the tim counter. c ounting resumes when tstop is cleared. reset sets t he tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before enteri ng wait mode if the tim is required to exit wait mode. trst ? tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no ef fect on any other registers. counting resumes from $0000 . trst is cleared automatically after the tim counter is rese t and always reads as l ogic zero. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps[2:0] ? prescaler select bits these read/write bits select either the tclk pin or one of the seven prescaler outputs as the i nput to the tim counter as table 11-2 shows. reset clears the ps[2:0] bits.
timer interface module (tim) i/o registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 157 11.10.2 tim counter registers (tcnth:tcntl) the two read-only tim counter register s contain the high and low bytes of the value in the ti m counter. reading the high byte (tcnth) latches the contents of t he low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tc ntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. table 11-2. prescaler selection ps2 ps1 ps0 tim clock source 0 0 0 internal bus clock 1 0 0 1 internal bus clock 2 0 1 0 internal bus clock 4 0 1 1 internal bus clock 8 1 0 0 internal bus clock 16 1 0 1 internal bus clock 32 1 1 0 internal bus clock 64 1 1 1 not available address: $000c tcnth bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:00000000 address: $000d tcntl bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:00000000 = unimplemented figure 11-4. tim counter registers (tcnth:tcntl)
timer interface module (tim) technical data mc68hc908ld60 ? rev. 1.1 158 timer interface module (tim) freescale semiconductor note: if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latc hed during the break. 11.10.3 tim counter modulo registers (tmodh:tmodl) the read/write tim modulo registers contain the modul o value for the tim counter. when the tim counter reaches t he modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next clo ck. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim c ounter modulo registers. note: reset the tim counter bef ore writing to the tim counter modulo registers. address: $000e tmodh bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset:11111111 address: $000f tmodl bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset:11111111 figure 11-5. tim counter modu lo registers (tmodh:tmodl)
timer interface module (tim) i/o registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 159 11.10.4 tim channel status and control registers (tsc0:tsc1) each of the tim channel status and control regi sters does the following: flags input captures and output compares enables input capture and output compare interrupts selects input capture, output compare, or pwm operation selects high, low, or t oggling output on output compare selects rising edge, fall ing edge, or any edge as the active input capture trigger selects output toggl ing on tim overflow selects 100% pwm duty cycle selects buffered or unbuffer ed output compare/pwm operation chxf ? chann el x flag bit when channel x is an inpu t capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is address: $0010 tsc0 bit 7654321bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset:00000000 address: $0013 tsc1 bit 7654321bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset:00000000 = unimplemented figure 11-6. tim channel status and control registers (tsc0:tsc1)
timer interface module (tim) technical data mc68hc908ld60 ? rev. 1.1 160 timer interface module (tim) freescale semiconductor an output compare channel, chxf is set when the value in the tim counter registers matche s the value in the ti m channel x registers. when tim cpu interrupt requests are enabled (chxie=1), clear chxf by reading the tim channel x status an d control register with chxf set and then writing a logic zero to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic zero to chxf has no effe ct. therefore, an interrupt request cannot be lost due to inadver tent clearing of chxf. reset clears the chxf bit. writing a logic one to chxf has no effect. 1 = input capture or out put compare on channel x 0 = no input capture or output compare on channel x chxie ? channel x in terrupt enable bit this read/write bi t enables tim cpu interrupt service requests on channel x. reset cl ears the chxie bit. 1 = channel x cpu inte rrupt requests enabled 0 = channel x cpu interr upt requests disabled msxb ? mode select bit b this read/write bit sele cts buffered output co mpare/pwm operation. msxb exists only in the tim channel 0 status and control register. setting ms0b disables the channel 1 status and control register and reverts tch1 to gen eral-purpose i/o. reset clears the msxb bit. 1 = buffered output com pare/pwm operation enabled 0 = buffered output compar e/pwm operation disabled msxa ? mode select bit a when elsxb:a 00, this read/write bit se lects either input capture operation or unbuffered outp ut compare/pwm operation. see table 11-3 . 1 = unbuffered output compare/pwm operation 0 = input capt ure operation when elsxb:a = 00, this read/write bit selects the in itial output level of the tchx pin. (see table 11-3 .) reset clears the msxa bit. 1 = initial output level low 0 = initial output level high
timer interface module (tim) i/o registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 161 note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bi ts in the tim status and control register (tsc). elsxb and elsxa ? edge/level select bits when channel x is an i nput capture channel, th ese read/write bits control the active edge- sensing logic on channel x. when channel x is an output co mpare channel, elsxb and elsxa control the channel x output beh avior when an output compare occurs. when els0b and els0a are both cl ear, channel 0 is not connected to the clamp/tch0 pin. the pin is available as the clamp output of the sync processor. table 11-3 shows how elsxb and elsx a work. reset clears the elsxb and elsxa bits. note: before enabling a tim ch annel register for input capture operation, make sure that the tchx pin is st able for at leas t two bus clocks. table 11-3. mode, edge, and level selection msxb msxa elsxb elsxa mode configuration x0 0 0 output preset pin is clamp of sync processor (1) ; initial output level high notes : 1. for clamp/tch0 pin only. x1 0 0 pin is clamp of sync processor (1) ; initial output level low 00 0 1 input capture capture on rising edge only 0 0 1 0 capture on falling edge only 0 0 1 1 capture on rising or falling edge 01 0 1 output compare or pwm toggle output on compare 0 1 1 0 clear output on compare 0 1 1 1 set output on compare 1x 0 1buffered output compare or buffered pwm toggle output on compare 1 x 1 0 clear output on compare 1 x 1 1 set output on compare
timer interface module (tim) technical data mc68hc908ld60 ? rev. 1.1 162 timer interface module (tim) freescale semiconductor tovx ? toggle-on-overflow bit when channel x is an output compar e channel, this read/write bit controls the behavior of the channel x output when t he tim counter overflows. when channel x is an i nput capture channel, tovx has no effect. reset clear s the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not t oggle on tim counter overflow. note: when tovx is set, a tim counter overflow takes precedence over a channel x output compare if bot h occur at the same time. chxmax ? channel x ma ximum duty cycle bit when the tovx bit is at logic zero, setting the chxmax bit forces the duty cycle of buffered and unbuffe red pwm signals to 100%. as figure 11-7 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 11-7. chxmax latency 11.10.5 tim channel registers (tch0h/l:tch1h/l) these read/write registers contain the captured tim counter value of the input capture function or the outp ut compare value of the output compare function. the state of the tim channel register s after reset is unknown. in input capture mode (m sxb:msxa = 0:0), reading the high byte of the tim channel x registers (t chxh) inhibits input c aptures until the low byte (tchxl) is read. output overflow tchx period chxmax overflow overflow overflow overflow compare output compare output compare output compare
timer interface module (tim) i/o registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor timer interface module (tim) 163 in output compare mode (msxb:msxa 0:0), writing to the high byte of the tim channel x regist ers (tchxh) inhibits out put compares until the low byte (tchxl) is written. address: $0011 tch0h bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset address: $0012 tch0l bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset address: $0014 tch1h bit 7654321bit 0 read: bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 write: reset: indeterminate after reset address: $0015 tch1l bit 7654321bit 0 read: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 write: reset: indeterminate after reset figure 11-8. tim channel regi sters (tch0h/l:tch1h/l)
timer interface module (tim) technical data mc68hc908ld60 ? rev. 1.1 164 timer interface module (tim) freescale semiconductor
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor pulse width modulator (pwm) 165 technical data ? mc68hc908ld60 section 12. pulse width modulator (pwm) 12.1 contents 12.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 12.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 12.4 pwm registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 12.4.1 pwm data registers 0 to 7 (0 pwm?7pwm). . . . . . . . . . . 167 12.4.2 pwm control register (pwmcr) . . . . . . . . . . . . . . . . . . . 168 12.2 introduction eight 8-bit pwm channels are av ailable on the mc68hc908ld60. channels 0 to 7 are shared with port- b i/o pins under t he control of the pwm control register. 12.3 functional description each 8-bit pwm channel is composed of an 8-bit register which contains a 5-bit pwm in m sb portion and a 3-bit binary rate multiplier (brm) in lsb portion. there are eight pwm data registers, controlling each pwm channel. the value program med in the 5-bit pwm portion will determine the pulse length of t he output. the clock to the 5-bit pwm portion is the system bus clock, the r epetition rate of the out put is hence 187.5khz at 6mhz clock. the 3-bit brm will generate a number of narro w pulses which are equally distributed among an 8-pwm-cy cle frame. the number of pulses generated is equal to the number program med in the 3-bit brm portion. example of the waveforms are shown in figure 12-4 .
pulse width modulator (pwm) technical data mc68hc908ld60 ? rev. 1.1 166 pulse width modulator (pwm) freescale semiconductor combining the 5-bit pwm together wit h the 3-bit brm, the average duty cycle at the output will be (m+n/8)/32, where m is the cont ent of the 5-bit pwm portion, and n is t he content of the 3-bit brm portion. using this mechanism, a true 8-bit resolution pwm type dac with reasonably high repetition rate can be obtained. the value of each pwm data register is continuously com pared with the content of an internal counter to determine the state of each pwm channel output pin. double buffering is not used in this pwm design. addr.register name bit 7654321bit 0 $0070 pwm0 data register (0pwm) read: 0pwm4 0pwm3 0pwm2 0pwm1 0pwm0 0brm2 0brm1 0brm0 write: $0071 pwm1 data register (1pwm) read: 1pwm4 1pwm3 1pwm2 1pwm1 1pwm0 1brm2 1brm1 1brm0 write: $0072 pwm2 data register (2pwm) read: 2pwm4 2pwm3 2pwm2 2pwm1 2pwm0 2brm2 2brm1 2brm0 write: $0073 pwm3 data register (3pwm) read: 3pwm4 3pwm3 3pwm2 3pwm1 3pwm0 3brm2 3brm1 3brm0 write: $0074 pwm4 data register (4pwm) read: 4pwm4 4pwm3 4pwm2 4pwm1 4pwm0 4brm2 4brm1 4brm0 write: $0075 pwm5 data register (5pwm) read: 5pwm4 5pwm3 5pwm2 5pwm1 5pwm0 5brm2 5brm1 5brm0 write: $0076 pwm6 data register (6pwm) read: 6pwm4 6pwm3 6pwm2 6pwm1 6pwm0 6brm2 6brm1 6brm0 write: $0077 pwm7 data register (7pwm) read: 7pwm4 7pwm3 7pwm2 7pwm1 7pwm0 7brm2 7brm1 7brm0 write: $0078 pwm control register (pwmcr) read: pwm7e pwm6e pwm5e pwm4e pwm3e pwm2e pwm1e pwm0e write: reset:00000000 figure 12-1. pwm i/o register summary
pulse width modulator (pwm) pwm registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor pulse width modulator (pwm) 167 12.4 pwm registers the pwm module uses of nine registers for data and control functions. pwm data registers ($0070?$0077) pwm control r egister ($0078) 12.4.1 pwm data registers 0 to 7 (0pwm?7pwm) the output waveform of the eight pw m channels are each configured by an 8-bit register, which contains a 5-bit pwm in msb portion and a 3-bit binary rate multiplier (brm) in lsb portion xpwm4?xpwm0 ? pwm bits the value programmed in the 5-bi t pwm portion will determine the pulse length of t he output. the clock to the 5-bit pwm portion is the system bus clock, the repetition rate of the output is hence f op 32. examples of pwm output waveforms are shown in figure 12-4 . xbrm2?xbrm0 ? binary rate multiplier bits the 3-bit brm will generate a number of narro w pulses which are equally distributed am ong an 8-pwm-cycle fr ame. the number of pulses generated is equal to the number progr ammed in the 3-bit brm portion. examples of pwm ou tput waveforms are shown in figure 12-4 . address: $0070?$0077 bit 7654321bit 0 read: xpwm4 xpwm3 xpwm2 xpwm1 xpwm0 xbrm2 xbrm1 xbrm0 write: reset:00000000 figure 12-2. pwm data regi sters 0 to 7 (0pwm?7pwm)
pulse width modulator (pwm) technical data mc68hc908ld60 ? rev. 1.1 168 pulse width modulator (pwm) freescale semiconductor 12.4.2 pwm control register (pwmcr) pwm7e?pwm0e ? pwm output enable setting a bit to 1 will enable th e corresponding pwm channel to use as pwm output. a zero configures the corresponding pwm pin as a standard i/o port pin. re set clears these bits. 1 = port pin configured as pwm output 0 = port pin configured as standard i/o port pin. address: $0078 bit 7654321bit 0 read: pwm7e pwm6e pwm5e pwm4e pwm3e pwm2e pwm1e pwm0e write: reset:00000000 figure 12-3. pwm cont rol register (pwmcr) table 12-1. pwm channel s and port i/o pins port pin pwm channel control bit ptb0 pwm0 pwm0e ptb1 pwm1 pwm1e ptb2 pwm2 pwm2e ptb3 pwm3 pwm3e ptb4 pwm4 pwm4e ptb5 pwm5 pwm5e ptb6 pwm6 pwm6e ptb7 pwm7 pwm7e
pulse width modulator (pwm) pwm registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor pulse width modulator (pwm) 169 figure 12-4. 8-bit pwm output waveforms m=$00 1 pwm cycle = 32t m=$01 m=$0f m=$1f t=1 cpu clock period (0.167ms if cpu clock=6mhz) pulse inserted at end of pwm cycle n pwm cycles where pulses are inserted in a 8-cycle frame number of inserted pulses in a 8-cycle frame xx1 4 1 x1x 2, 6 2 1xx 1, 3, 5, 7 4 31t 16t 16t 31t t m = value set in 5-bit pwm (bit3-bit7) n = value set in 3-bit brm (bit0-bit2) t depends on setting of n.
pulse width modulator (pwm) technical data mc68hc908ld60 ? rev. 1.1 170 pulse width modulator (pwm) freescale semiconductor
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 171 technical data ? mc68hc908ld60 section 13. analog-to-digital converter (adc) 13.1 contents 13.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 13.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 13.4.1 adc port i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13.4.2 voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 13.4.3 conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 13.4.4 continuous conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 13.4.5 accuracy and precision . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 13.5 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 13.6 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 13.6.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 13.6.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 13.7 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.7.1 adc analog power pin (vdda). . . . . . . . . . . . . . . . . . . . . 176 13.7.2 adc analog ground pin (vssa) . . . . . . . . . . . . . . . . . . . .176 13.7.3 adc voltage reference high pin (v rh) . . . . . . . . . . . . . . 176 13.7.4 adc voltage reference low pin ( vrl). . . . . . . . . . . . . . . 176 13.7.5 adc voltage in ( adcvin) . . . . . . . . . . . . . . . . . . . . . . . . . 176 13.8 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 13.8.1 adc status and control register. . . . . . . . . . . . . . . . . . . .177 13.8.2 adc data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 13.8.3 adc input clock register . . . . . . . . . . . . . . . . . . . . . . . . . 179
analog-to-digital converter (adc) technical data mc68hc908ld60 ? rev. 1.1 172 analog-to-digital converter (adc) freescale semiconductor 13.2 introduction this section describes the analog-to-digital converter (adc). the adc is a 6-channel 8-bit succe ssive approximation adc. 13.3 features features of the ad c module include: six channels with multiplexed input linear successive approximation 8-bit resolution single or cont inuous conversion conversion complete flag or conversion complete interrupt selectable adc clock addr.register name bit 7654321bit 0 $003b adc status and control register (adscr) read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 $003c adc data register (adr) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: unaffected after reset $003d adc input clock register (adiclk) read: adiv2 adiv1 adiv0 00000 write: reset:00000000 = unimplemented figure 13-1. adc i/o register summary
analog-to-digital converter (adc) functional description mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 173 13.4 functional description six adc channels are avail able for sampling exter nal sources at pins ptc5?ptc0. an analog multiplexer al lows the single adc converter to select one of the six adc channels as adc vo ltage input (adcvin). adcvin is converted by the successi ve approximation register-based counters. the adc resolu tion is eight bits. when the conversion is completed, adc puts the result in the adc data register and sets a flag or generates an interrupt. figure 13-2 shows a block diagram of the adc. figure 13-2. adc block diagram internal data bus interrupt logic channel select adc clock generator conversion complete adc voltage in adcvin adc clock bus clock adch[4:0] adc data register adiv[2:0] adiclk aien coco disable disable adc channel x read ddrc write ddrc reset write ptc read ptc ptcx/adcx ddrcx ptcx (1 of 6 channels)
analog-to-digital converter (adc) technical data mc68hc908ld60 ? rev. 1.1 174 analog-to-digital converter (adc) freescale semiconductor 13.4.1 adc port i/o pins ptc5/adc5?ptc0/adc0 are general-pur pose i/o pins that are shared with the adc channels. th e channel select bits, adch[4:0], in the adc status and control regist er define which adc ch annel/port pin will be used as the input signal. the adc overri des the port i/o logic by forcing that pin as input to the adc. the remaining adc channels/port pins are controlled by the port i/o logic and c an be used as general-purpose i/o. writes to the port register or ddr will not have any affect on the port pin that is selected by the ad c. read of a port pin which is in use by the adc will return a logic 0 if the corresponding ddr bit is at logic 0. if the ddr bit is at logic 1, the value in the port data latch is read. 13.4.2 voltage conversion when the input voltage to the adc equals to vrh, the adc converts the signal to $ff (full scale ). if the input volt age equals to vrl, the adc converts it to $00. input voltages between vrh a nd vrl is a straight-line linear conversion. all other input volta ges will result in $ff if greater than vrh and $00 if less than vrl. note: input voltage should not exceed the analog supply voltages. 13.4.3 conversion time sixteen adc internal cl ocks are required to perfo rm one conversion. the adc starts a conversion on the first rising edge of the adc internal clock immediately following a wr ite to the adscr. if the adc internal clock is selected to run at 1mhz, then one conversion will take 16 s to complete. with a 1mhz adc internal clock t he maximum sample rate is 62.5khz. 16 to17 adc cycles conversion time = adc frequency number of bus cycles = conversion time bus frequency
analog-to-digital converter (adc) interrupts mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 175 13.4.4 continuous conversion in the continuous conv ersion mode, the adc cont inuously converts the selected channel filling t he adc data register wi th new data after each conversion. data from the previous conversion will be overwritten whether that data has been read or not . conversions will continue until the adco bit is clear ed. the conversion complete bit, coco, in the adc status and control register is set after each conversion and can be cleared by writing to the adc status and control regi ster or reading of the adc data register. 13.4.5 accuracy and precision the conversion process is monot onic and has no missing codes. 13.5 interrupts when the aien bit is se t, the adc module is capable of generating a cpu interrupt after each adc conversion. a cpu interrupt is generated if the coco bit is at logic 0. the coco bit is not used as a conversion complete flag when interrupts are enabled. the interr upt vector is defined in table 2-1 . v ector addresses . 13.6 low-power modes the wait and stop in struction can put th e mcu in low-power consumption standby modes. 13.6.1 wait mode the adc continues norma l operation during wait mode. any enabled cpu interrupt request fro m the adc can bring t he mcu out of wait mode. if the adc is not required to bring the mcu out of wait mode, power down the adc by se tting the adch[4:0] bits in the adc status and control register to l ogic 1?s before executi ng the wait instruction.
analog-to-digital converter (adc) technical data mc68hc908ld60 ? rev. 1.1 176 analog-to-digital converter (adc) freescale semiconductor 13.6.2 stop mode the adc module is inactive after the execution of a stop instruction. any pending conversion is aborted. adc conver sions resume when the mcu exits stop mode. allow one conver sion cycle to stabilize the analog circuitry before attempting a new adc conversion af ter exiting stop mode. 13.7 i/o signals the adc module has six channels that are shared with port c i/o pins, ptc5/adc5?ptc0/adc0. 13.7.1 adc analog power pin (vdda) the adc analog portion uses vdda as its power pin. connect the vdda pin to the same vo ltage potential as vdd. external filtering may be necessary to ensure cl ean vdda for good results. note: route vdda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. 13.7.2 adc analog ground pin (vssa) the adc analog portion uses vssa as its gr ound pin. connect the vssa pin to the same vo ltage potential as vss. 13.7.3 adc voltage reference high pin (vrh) vrh is the high voltage reference for the adc. 13.7.4 adc voltage reference low pin (vrl) vrl is the low voltage reference for the adc. 13.7.5 adc voltage in (adcvin) adcvin is the input volt age signal from one of the six adc channels to the adc module.
analog-to-digital converter (adc) i/o registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 177 13.8 i/o registers three i/o registers control and monitor adc operation: adc status and cont rol register (adscr) adc data register (adr) adc input clock register (adiclk) 13.8.1 adc status and control register function of the adc stat us and control register is described here. coco ? conversions complete bit when the aien bit is a l ogic 0, the coco is a read-only bit which is set each time a conversion is comple ted. this bit is cleared whenever the adc status and contro l register is written, or whenever the adc data register is read. reset clears this bit. when the aien bit is a logic 1 (cpu interrupt enabled), the coco is a read-only bit, and will always be lo gic 0 when read. 1 = conversion completed (aien = 0) 0 = conversion not co mpleted (aien = 0) aien ? adc interrupt enable bit when this bit is set, an interrupt is generated at the end of an adc conversion. the interrupt signal is cl eared when the dat a register is read or the status and c ontrol register is writ ten. reset clears the aien bit. 1 = adc interrupt enabled 0 = adc interrupt disabled address: $003b bit 7654321bit 0 read: coco aien adco adch4 adch3 adch2 adch1 adch0 write: reset:00011111 = unimplemented figure 13-3. adc status and contro l register (adscr)
analog-to-digital converter (adc) technical data mc68hc908ld60 ? rev. 1.1 178 analog-to-digital converter (adc) freescale semiconductor adco ? adc continuous conversion bit when set, the adc will convert sa mples continuously and update the adr register at the end of each conversion. only one conversion is allowed when this bit is cleared. reset clears the adco bit. 1 = continuous adc conversion 0 = one adc conversion adch[4:0] ? adc channel select bits adch[4:0] form a 5-bit field which is used to select one of the adc channels or reference voltages. th e five channel select bits are detailed in the table 13-1 . note: care should be taken when using a port pin as both an analog and a digital input simultaneous ly to prevent switchin g noise from corrupting the analog signal. note: recovery from the disabled stat e requires one conversion cycle to stabilize. table 13-1. mux channel select adch4 adch3 adch2 ad ch1 adch0 adc channel input select 00000 adc0 ptc0/adc0 00001 adc1 ptc1/adc1 00010 adc2 ptc2/adc2 00011 adc3 ptc3/adc3 00100 adc4 ptc4/adc4 00101 adc5 ptc5/adc5 00110 unused (1) ? 11010 11011 ? reserved 11 1 0 0 ? unused 11 1 0 1 vrh 11 1 1 0 vrl 11 1 1 1 adc power off notes : 1. if any unused channels are selected, the resulting adc conversion will be unknown.
analog-to-digital converter (adc) i/o registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor analog-to-digital converter (adc) 179 13.8.2 adc data register one 8-bit result regist er, adc data register (a dr), is provided. this register is updated each time an adc conversion completes. 13.8.3 adc input clock register the adc input clock register (adiclk) select s the clock frequency for the adc. adiv[2:0] ? adc clock prescaler bits adiv[2:0] form a 3-bit field which selects the divide ratio used by the adc to generate the in ternal adc clock. table 13-2 shows the available clock configurations. the adc clock shou ld be set to approximately 1mhz. address: $003c bit 7654321bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset = unimplemented figure 13-4. adc data register (adr) address: $003d bit 7654321bit 0 read: adiv2 adiv1 adiv0 00000 write: reset:00000000 = unimplemented figure 13-5. adc input cl ock register (adiclk)
analog-to-digital converter (adc) technical data mc68hc908ld60 ? rev. 1.1 180 analog-to-digital converter (adc) freescale semiconductor table 13-2. adc clock divide ratio adiv2 adiv1 adiv0 adc clock rate 0 0 0 adc input clock 1 0 0 1 adc input clock 2 0 1 0 adc input clock 4 0 1 1 adc input clock 8 1 x x adc input clock 16 x = don?t care
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor multi-master iic interface (mmiic) 181 technical data ? mc68hc908ld60 section 14. multi-master iic interface (mmiic) 14.1 contents 14.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 14.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 14.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 14.5 multi-master iic registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 14.5.1 multi-master iic address regist er (mmadr) . . . . . . . . . . 184 14.5.2 multi-master iic control register (mmcr) . . . . . . . . . . . . 185 14.5.3 multi-master iic ma ster control register (mimcr) . . . . . . 186 14.5.4 multi-master iic stat us register (mmsr) . . . . . . . . . . . . . 188 14.5.5 multi-master iic data transm it register (mmdtr) . . . . . . 190 14.5.6 multi-master iic data receiv e register (mmdrr ) . . . . . . 191 14.6 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . 192 14.2 introduction this multi-master iic (mmi ic) interface is designe d for internal serial communication between the mcu and other iic devices. a hardware circuit generates "start" and "stop" signal, while byte by byte data transfer is interrupt driven by the so ftware algorithm. therefore, it can greatly help the software in dealin g with other devices to have higher system efficiency in a typi cal digital monitor system. this module not only can be applied in internal co mmunications, but can also be used as a typical command reception serial bus for factory setup and alignment purposes. it also prov ides the flexib ility of hooking additional devices to an existing sys tem for future expansion without adding extra hardware.
multi-master iic interface (mmiic) technical data mc68hc908ld60 ? rev. 1.1 182 multi-master iic interface (mmiic) freescale semiconductor this multi-master iic module uses t he iicscl clock lin e and the iicsda data line to communicate wi th external ddc host or iic interface. these two pins are shared with port pins ptd6 and ptd7 respectively. the outputs of iicsda and ii cscl pins are open-dr ain type ? no clamping diode is connected betwe en the pin and internal v dd . the maximum data rate typically is 750k-bps. the maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400pf. 14.3 features compatibility with multi-master iic bus standard software controllable a cknowledge bit generation interrupt driven byte by byte data transfer calling address iden tification interrupt auto detection of r/w bit and switching of transmit or receive mode detection of start, repeat ed start, and stop signals auto generation of start and stop condition in master mode arbitration loss detection and no -ack awareness in master mode 8 selectable baud ra te master clocks automatic recognition of th e received acknowledge bit 14.4 i/o pins the mmiic module uses two i/o pins , shared with standard port i/o pins. the full name of the mmiic i/o pins are listed in table 14-1 . the generic pin name appear in the text that follows. table 14-1. pin name conventions mmiic generic pin names: full mcu pin names: pin selected for iic function by: sda ptd7/iicsda iicdate bit in pdcr ($0069) scl ptd6/iicscl iicscle bit in pdcr ($0069)
multi-master iic interface (mmiic) multi-master iic registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor multi-master iic interface (mmiic) 183 14.5 multi-master iic registers six registers are associ ated with the multi-master iic module, they are outlined in the following sections. addr.register name bit 7654321bit 0 $006a multi-master iic master control register (mimcr) read: mmalif mmnakif mmbb mmast mmrw mmbr2 mmbr1 mmbr0 write: 0 0 reset:00000000 $006b multi-master iic address register (mmadr) read: mmad7 mmad6 mmad5 mmad4 mmad3 mmad2 mmad1 mmextad write: reset:10100000 $006c multi-master iic control register (mmcr) read: mmen mmien 00 mmtxak 000 write: reset:00000000 $006d multi-master iic status register (mmsr) read: mmrxif mmtxif mmatch mmsrw mmrxak 0 mmtxbe mmrxbf write: 0 0 reset:00001010 $006e multi-master iic data transmit register (mmdtr) read: mmtd7 mmtd6 mmtd5 mmtd4 mmtd3 mmtd2 mmtd1 mmtd0 write: reset:11111111 $006f multi-master iic data receive register (mmdrr) read: mmrd7 mmrd6 mmrd5 mmrd4 mmrd3 mmrd2 mmrd1 mmrd0 write: reset:00000000 = unimplemented figure 14-1. mmiic i/ o register summary
multi-master iic interface (mmiic) technical data mc68hc908ld60 ? rev. 1.1 184 multi-master iic interface (mmiic) freescale semiconductor 14.5.1 multi-master iic address register (mmadr) mmad[7:1] ? multi-master address these seven bits can be the mmiic interface? s own specific slave address in slave mode or the call ing address when in master mode. software must update it as the calling address while entering the master mode and restore it s own slave address af ter the master mode is relinquished. reset se ts a default value of $a0. mmextad ? multi-mast er expanded address this bit is set to ex pand the address of the mmiic in slave mode. when set, the mmiic will acknowledge the general call address $00 and the matched 4-bit address, mm ad[7:4]. reset clears this bit. for example, when mm adr is configured as: the mmiic module will res pond to the ca lling address: or the general calling address: where x = don?t care; bit 0 of the ca lling address is t he mmrw bit from the calling master. 1 = mmiic responds to address $00 and $mmad[7:4] 0 = mmiic responds to address $mmad[7:1] address: $006b bit 7654321bit 0 read: mmad7 mmad6 mmad5 mmad4 mmad3 mmad2 mmad1 mmextad write: reset:10100000 figure 14-2. multi- master iic address register (mmadr) mmad7 mmad6 mmad5 mmad4 mmad3 mmad2 mmad 1 mmextad 1101xxx1 bit 765432bit 1 1101xxx 0000000
multi-master iic interface (mmiic) multi-master iic registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor multi-master iic interface (mmiic) 185 14.5.2 multi-master iic control register (mmcr) mmen ? multi-master iic enable this bit is set to enable the multi-mast er iic module. when mmen = 0, module is disabled and all flags will restor e to its power- on default states. reset clears this bit. 1 = mmiic module enabled 0 = mmiic module disabled mmien ? multi-master iic interrupt enable when this bit is set, the mmtx if, mmrxif, mmalif, and mmnakif flags are enabled to generate an in terrupt request to the cpu. when mmien is cleared, the these flags are prevented from generating an interrupt request. re set clears this bit. 1 = mmtxif, mmrxif, mmalif, and/or mmnakif bit set will generate interrupt request to cpu 0 = mmtxif, mmrxif, mmalif, a nd/or mmnakif bit set will not generate interrupt request to cpu mmtxak ? transmit acknowledge enable this bit is set to disable the mmiic from sending out an acknowledge signal to the bus at the 9th clock bit after receiving 8 data bits. when mmtxak is cleared, an acknowledge signal wi ll be sent at the 9th clock bit. reset clears this bit. 1 = mmiic does not send ackno wledge signals at 9th clock bit 0 = mmiic sends acknowledge signal at 9th clock bit address: $006c bit 7654321bit 0 read: mmen mmien 00 mmtxak 000 write: reset:00000000 = unimplemented figure 14-3. multi-master iic control register (mmcr)
multi-master iic interface (mmiic) technical data mc68hc908ld60 ? rev. 1.1 186 multi-master iic interface (mmiic) freescale semiconductor 14.5.3 multi-master iic master control register (mimcr) mmalif ? multi-master arbi tration lost interrupt flag this flag is set when software atte mpt to set mmast but the mmbb has been set by detecting the start condition on the lin es or when the mmiic is transmitting a "1" to sd a line but detecte d a "0" from sda line in master mode ? an arbitration loss. this bit generates an interrupt request to the cpu if th e mmien bit in mmcr is also set. this bit is cleared by writi ng "0" to it or by reset. 1 = lost arbitrati on in master mode 0 = no arbitration lost mmnakif ? no acknowledge interrupt flag this flag is only set in master mode (mmast = 1) when there is no acknowledge bit detected after one data byte or calling address is transferred. this flag also clear s mmast. mmnakif generates an interrupt request to cpu if the mmie n bit in mmcr is also set. this bit is cleared by writing "0" to it or by reset. 1 = no acknowl edge bit detected 0 = acknowledg e bit detected mmbb ? bus busy flag this flag is set after a start conditi on is detected (bus busy), and is cleared when a stop condition (bus idle) is detected or the mmiic is disabled. reset clears this bit. 1 = start condition detected 0 = stop condition detected or mmiic is disabled address: $006a bit 7654321bit 0 read: mmalif mmnakif mmbb mmast mmrw mmbr2 mmbr1 mmbr0 write: 0 0 reset:00000000 figure 14-4. multi-master iic ma ster control register (mimcr)
multi-master iic interface (mmiic) multi-master iic registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor multi-master iic interface (mmiic) 187 mmast ? master control bit this bit is set to initia te a master mode transf er. in master mode, the module generates a star t condition to the sda and scl lines, followed by sending the calli ng address stored in mmadr. when the mmast bit is cleared by mmnakif set (no acknowledge) or by software, the mo dule generates the stop condition to the lines after the current byte is transmitted. if an arbitration loss occurs (mmali f = 1), the module reverts to slave mode by clearing mmast, and releasing sda and scl lines immediately. this bit is cleared by writi ng "0" to it or by reset. 1 = master mode operation 0 = slave mode operation mmrw ? master read/write this bit will be tr ansmitted out as bit 0 of th e calling address when the module sets the mmast bit to ent er master mode. the mmrw bit determines the transfer direction of the data bytes that follows. when it is "1", the module is in master receive mode. when it is "0", the module is in master transmit mode. reset clears this bit. 1 = master mode receive 0 = master mode transmit mmbr2?mmbr0 ? baud rate select these three bits select one of eigh t clock rates as the master clock when the module is in master mode. since this master clock is deri ved the cpu bus cl ock, the user program should not execute the wa it instruction when the mmiic module in master mode. this will cause the sda and scl lines to hang, as the wait instruction places the mcu in wait mode, with cpu clock is halted. these bits are cleared upon reset. (see table 14-2 . baud rate select .)
multi-master iic interface (mmiic) technical data mc68hc908ld60 ? rev. 1.1 188 multi-master iic interface (mmiic) freescale semiconductor 14.5.4 multi-master iic status register (mmsr) mmrxif ? multi-master ii c receive interrupt flag this flag is set after the data receiv e register (mmdrr) is loaded with a new received data. once the mm drr is loaded with received data, no more received data can be loaded to the mmdrr register until the cpu reads the data from the mmdrr to clear mmrxbf flag. mmrxif generates an in terrupt request to cpu if the mmien bit in mmcr is also set. this bit is cleared by writing "0" to it or by reset; or when the mmen = 0. 1 = new data in data re ceive register (mmdrr) 0 = no data received table 14-2. baud rate select mmbr2 mmbr1 mmbr0 baud rate 000 750k 001 375k 0 1 0 187.5k 011 93.75k 100 46.875k 101 23.437k 110 11.719k 1 1 1 5.859k note: cpu bus clock is external clock 4 = 6mhz address: $006d bit 7654321bit 0 read: mmrxif mmtxif mmatch mmsrw mmrxak 0 mmtxbe mmrxbf write: 0 0 reset:00001010 = unimplemented figure 14-5. multi-master ii c status register (mmsr)
multi-master iic interface (mmiic) multi-master iic registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor multi-master iic interface (mmiic) 189 mmtxif ? multi-master transmit interrupt flag this flag is set when data in the data transmit regi ster (mmdtr) is downloaded to the output circuit, and that new data ca n be written to the mmdtr. mmtxif generates an in terrupt request to cpu if the mmien bit in mmcr is also set. this bit is cleared by writing "0" to it or when the mmen = 0. 1 = data transfer completed 0 = data transfer in progress mmatch ? multi-master address match this flag is set when the received data in the data receive register (mmdrr) is an calling address whic h matches with the address or its extended addresses (mmextad=1) specified in the mmadr register. 1 = received address matches mmadr 0 = received address does not match mmsrw ? multi-master slave read/write this bit indicates the data direction when the module is in slave mode. it is updated after t he calling address is rece ived from a master device. mmsrw = 1 when the calling ma ster is reading data from the module (slave transmit mode). mmsrw = 0 when the master is writing data to the m odule (receive mode). 1 = slave mode transmit 0 = slave mode receive mmrxak ? multi-master receive acknowledge when this bit is clear ed, it indicate s an acknowledge signal has been received after the comp letion of 8 data bits transmission on the bus. when mmrxak is set, it indicates no acknow ledge signal has been detected at the 9th clo ck; the module will releas e the sda line for the master to generate "stop" or "repeated start" condi tion. reset sets this bit. 1 = no acknowledge signal received at 9th clock bit 0 = acknowledge signal re ceived at 9th clock bit
multi-master iic interface (mmiic) technical data mc68hc908ld60 ? rev. 1.1 190 multi-master iic interface (mmiic) freescale semiconductor mmtxbe ? multi-master transmit buffer empty this flag indicates the status of th e data transmit r egister (mmdtr). when the cpu writes the data to the mmdtr, the mmtxbe flag will be cleared. mmtxbe is se t when mmdtr is empt ied by a transfer of its data to the out put circuit. reset sets this bit. 1 = data transmit register empty 0 = data transmit register full mmrxbf ? multi-master receive buffer full this flag indicates the status of th e data receive register (mmdrr). when the cpu reads the data from the mmdrr, the mmrxbf flag will be cleared. mmrx bf is set when mmdrr is full by a transfer of data from the input circ uit to the mmdrr. re set clears this bit. 1 = data receive register full 0 = data receive register empty 14.5.5 multi-master iic data transmit register (mmdtr) when the mmiic module is enabled, mmen = 1, data written into this register depends on whether module is in master or slave mode. in slave mode, the data in mmdtr will be transferr ed to the out put circuit when: the module detects a matched calling addres s (mmatch = 1), with the calling master requesting data (mmsrw = 1); or the previous data in the output circuit has be tr ansmitted and the receiving master returns an a cknowledge bit, indicated by a received acknowl edge bit (mmrxak = 0). address: $006e bit 7654321bit 0 read: mmtd7 mmtd6 mmtd5 mmtd4 mmtd3 mmtd2 mmtd1 mmtd0 write: reset:11111111 figure 14-6. multi-master iic da ta transmit register (mmdtr)
multi-master iic interface (mmiic) multi-master iic registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor multi-master iic interface (mmiic) 191 if the calling master does not re turn an acknowledge bit (mmrxak = 1), the module will release the sda line for master to generate a "stop" or "repeated start" condition. the data in the mmdtr will not be transferred to the output circuit until the nex t calling from a master. the transmit buffer empty flag remains cleared (mmtxbe = 0). in master mode, the dat a in mmdtr will be tr ansferred to the output circuit when: the module receives an acknow ledge bit (mmr xak = 0), after setting master transmit m ode (mmrw = 0), and the calling address has been transmitted; or the previous data in the output circuit has be tr ansmitted and the receiving slave retu rns an acknowledge bi t, indicated by a received acknowl edge bit (mmrxak = 0). if the slave does not return an acknowledge bit (mmrxak = 1), the master will gener ate a "stop" or "repeated start" condition. th e data in the mmdtr will not be trans ferred to the output circuit. the transmit buffer empty flag remains cleared (mmtxbe = 0). the sequence of events for slave tr ansmit and master transmit are illustrated in figure 14-8 . 14.5.6 multi-master iic data receive register (mmdrr) when the mmiic module is enabled, mmen = 1, data in this read-only register depends on whether module is in master or slave mode. address : $006f bit 7654321bit 0 read: mmrd7 mmrd6 mmrd5 mmrd4 mmrd3 mmrd2 mmrd1 mmrd0 write: reset:00000000 = unimplemente d figure 14-7. multi-master iic data receive r egister (mmdrr)
multi-master iic interface (mmiic) technical data mc68hc908ld60 ? rev. 1.1 192 multi-master iic interface (mmiic) freescale semiconductor in slave mode, t he data in mmdrr is: the calling address from the ma ster when the address match flag is set (mmatch = 1); or the last data received when mmatch = 0. in master mode, the data in the mmdrr is: the last data received. when the mmdrr is read by the cpu, the receive buffer full flag is cleared (mmrxbf = 0), and the next re ceived data is loaded to the mmdrr. each time when new data is loaded to the mmdrr, the mmrxif interrupt flag is set, indicati ng that new data is available in mmdrr. the sequence of events for slave receive and master receive are illustrated in figure 14-8 . 14.6 programming considerations when the mmiic module detects an arbi tration loss in ma ster mode, it will release both sda and scl lines im mediately. but if there are no further stop condi tions detected, the module will hang up. therefore, it is recommended to have time-out soft ware to recover from such ill condition. the software can start the ti me-out counter by looking at the mmbb (bus busy) flag in the mimcr and rese t the counter on the completion of one byte tr ansmission. if a time-out occur, software can clear the mmen bit (disable mmiic module) to rele ase the bus, and hence clearing the mm bb flag. this is the onl y way to clear the mmbb flag by software if the module hangs up due to a no stop condition received. the mmiic c an resume operation again by setting the mmen bit.
multi-master iic interface (mmiic) programming considerations mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor multi-master iic interface (mmiic) 193 figure 14-8. data transf er sequences for master/sla ve transmit/receive modes start address ack tx data1 mmtxbe=0 mmrw=0 mmast=1 mmtxif=1 mmtxbe=1 mmnakif=1 mmast=0 mmtxbe=1 (a) master transmit mode (b) master receive mode (c) slave transmit mode mmtxif=1 mmtxbe=0 ack tx datan nak stop mmtxif=1 mmtxbe=1 start address ack rx data1 mmrxbf=0 mmast=1 mmtxbe=0 mmrxbf=1 mmrxif=1 mmnakif=1 mmast=0 mmrxif=1 mmrxbf=1 ack rx datan nak stop 1 start address ack tx data1 mmtxbe=1 mmrxbf=0 mmnakif=1 mmtxbe=0 mmtxbe=1 (d) slave receive mode mmtxif=1 ack tx datan nak stop mmrxbf=1 mmrxif=1 mmatch=1 mmsrw=1 mmtxif=1 mmtxbe=1 0 start address ack rx data1 mmrxbf=1 mmrxif=1 mmrxif=1 mmrxbf=1 ack rx datan nak stop mmtxbe=0 mmrxbf=0 mmrxbf=1 mmrxif=1 mmatch=1 mmsrw=0 data1 mmdrr datan mmdrr data1 mmdtr data2 mmdtr datan+2 mmdtr data1 mmdtr data2 mmdtr data3 mmdtr datan+2 mmdtr (dummy data mmdtr) mmrw=1 data1 mmdrr datan mmdrr 0 1 key: shaded data packets indicate a transmit by the mcu?s mmiic module
multi-master iic interface (mmiic) technical data mc68hc908ld60 ? rev. 1.1 194 multi-master iic interface (mmiic) freescale semiconductor
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor ddc12ab interface 195 technical data ? mc68hc908ld60 section 15. ddc12ab interface 15.1 contents 15.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 15.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 15.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 15.5 ddc protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 15.6 ddc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 15.6.1 ddc address register (dadr) . . . . . . . . . . . . . . . . . . . . . 198 15.6.2 ddc2 address register (d2adr) . . . . . . . . . . . . . . . . . . . 199 15.6.3 ddc control register (dcr) . . . . . . . . . . . . . . . . . . . . . . . 200 15.6.4 ddc master control register (d mcr) . . . . . . . . . . . . . . . 201 15.6.5 ddc status register (dsr) . . . . . . . . . . . . . . . . . . . . . . . . 204 15.6.6 ddc data transmit r egister (ddtr) . . . . . . . . . . . . . . . . 206 15.6.7 ddc data receive register (ddrr) . . . . . . . . . . . . . . . . . 207 15.7 programming considerations . . . . . . . . . . . . . . . . . . . . . . . . . 208 15.2 introduction this ddc12ab interface module is used by the digital monitor to show its identification informat ion to the video contro ller. it contains ddc1 hardware and a two-wire, bidirectional serial bus which is fully compatible with multi-master ii c bus protocol to support ddc2ab interface. this module not only can be applied in internal co mmunications, but can also be used as a typical command reception serial bus for factory setup and alignment purposes. it also prov ides the flexib ility of hooking additional devices to an existing sys tem for future expansion without adding extra hardware.
ddc12ab interface technical data mc68hc908ld60 ? rev. 1.1 196 ddc12ab interface freescale semiconductor this ddc12ab module uses the ddcscl clock li ne and the ddcsda data line to communicate wi th external ddc host or iic interface. these two pins are shared with port pins ptd4 and ptd5 respectively. the outputs of ddcsda and ddcscl pins are open-drain type ? no clamping diode is connected bet ween the pin and internal v dd . the maximum data rate typically is 100 k-bps. the maximum communication length and the number of devices that can be c onnected are limited by a maximum bus capa citance of 400pf. 15.3 features ddc1 hardware compatibility with multi-master iic bus standard software controllable a cknowledge bit generation interrupt driven byte by byte data transfer calling address iden tification interrupt auto detection of r/w bit and switching of transmit or receive mode detection of start, repeat ed start, and stop signals auto generation of start and stop condition in master mode arbitration loss detection and no -ack awareness in master mode 8 selectable baud ra te master clocks automatic recognition of th e received acknowledge bit 15.4 i/o pins the ddc12ab module uses two i/o pi ns, shared with standard port i/o pins. the full name of the ddc 12ab i/o pins are listed in table 15-1 . the generic pin name appear in the text that follows. table 15-1. pin name conventions ddc12ab generic pin names: full mcu pin names: pin selected for ddc function by: sda ptd5/ddcsda ddcdate bit in pdcr ($0069) scl ptd4/ddcscl ddcscle bit in pdcr ($0069)
ddc12ab interface i/o pins mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor ddc12ab interface 197 addr.register name bit 7654321bit 0 $0016 ddc master control register (dmcr) read: alif nakif bb mast mrw br2 br1 br0 write: 00 reset:00000000 $0017 ddc address register (dadr) read: dad7 dad6 dad5 dad4 dad3 dad2 dad1 extad write: reset:10100000 $0018 ddc control register (dcr) read: den dien 00 txak sclien ddc1en 0 write: reset:00000000 $0019 ddc status register (dsr) read: rxif txif match srw rxak sclif txbe rxbf write: 0 0 0 reset:00001010 $001a ddc data transmit register (ddtr) read: dtd7 dtd6 dtd5 dtd4 dtd3 dtd2 dtd1 dtd0 write: reset:11111111 $001b ddc data receive register (ddrr) read: drd7 drd6 drd5 dr d4 drd3 drd2 drd1 drd0 write: reset:00000000 $001c ddc2 address register (d2adr) read: d2ad7 d2ad6 d2ad5 d2ad4 d2ad3 d2ad2 d2ad1 0 write: reset:00000000 = unimplemented figure 15-1. ddc i/o register summary
ddc12ab interface technical data mc68hc908ld60 ? rev. 1.1 198 ddc12ab interface freescale semiconductor 15.5 ddc protocols in ddc1 protocol comm unication, the module is in transmit mode. the data written to the transmi t register is continuou sly clocked out to the sda line by the rising edge of th e vsync input si gnal. during ddc1 communication, a falling transition on the sc l line can be detected to generate an interrupt to t he cpu for mode switching. in ddc2ab protocol co mmunication, the modu le can be either in transmit mode or in rece ive mode, contro lled by the calling master. in ddc2 protocol comm unication, the module wil l act as a standard iic module, able to act as a master or a slave device. 15.6 ddc registers seven registers are associated with the ddc module, t hey outlined in the following sections. 15.6.1 ddc address register (dadr) dad[7:1] ? ddc address these seven bits can be the ddc2 interface?s own specific slave address in slave mode or the call ing address when in master mode. software must update it as the calling address while entering the master mode and restore it s own slave address af ter the master mode is relinquished. reset se ts a default value of $a0. address: $0017 bit 7654321bit 0 read: dad7 dad6 dad5 dad4 dad3 dad2 dad1 extad write: reset:10100000 figure 15-2. ddc addr ess register (dadr)
ddc12ab interface ddc registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor ddc12ab interface 199 extad ? ddc expanded address this bit is set to exp and the address of the d dc in slave mode. when set, the ddc will acknowledge th e general call address $00 and the matched 4-bit addres s, dad[7:4]. reset clears this bit. for example, when d adr is configured as: the ddc module will respon d to the calling address: or the general calling address: where x = don?t care; bit 0 of the calling address is the mrw bit from the calling master. 1 = ddc responds to addr ess $00 and $dad[7:4] 0 = ddc responds to address $dad[7:1] 15.6.2 ddc2 address register (d2adr) d2ad[7:1] ? ddc2 address these seven bits represent the sec ond slave address for the ddc2bi protocol. d2ad[7:1] shoul d be set to the same value as dad[7:1] in dadr if user application do not use ddc2bi. reset clears all bits this register. dad7 dad6 dad5 dad4 dad3 dad2 dad 1 extad 1101xxx1 bit 765432bit 1 1101xxx 0000000 address: $001c bit 7654321bit 0 read: d2ad7 d2ad6 d2ad5 d2ad4 d2ad3 d2ad2 d2ad1 0 write: reset:00000000 figure 15-3. ddc2 addr ess register (d2adr)
ddc12ab interface technical data mc68hc908ld60 ? rev. 1.1 200 ddc12ab interface freescale semiconductor 15.6.3 ddc control register (dcr) den ? ddc enable this bit is set to ena ble the ddc module. w hen den = 0, module is disabled and all flags will restore to its power-o n default states. reset clears this bit. 1 = ddc module enabled 0 = ddc module disabled dien ? ddc interrupt enable when this bit is set, the txif, rxif, alif, and nakif flags are enabled to generate an inte rrupt request to the cpu. when dien is cleared, the these flag s are prevented from generating an interrupt request. reset clears this bit. 1 = txif, rxif, alif, and/or naki f bit set will generate interrupt request to cpu 0 = txif, rxif, alif, and/or n akif bit set will not generate interrupt request to cpu txak ? transmit a cknowledge enable this bit is set to dis able the ddc from sendi ng out an acknowledge signal to the bus at the 9th clock bit after receiving 8 data bits. when txak is cleared, an acknowledge si gnal will be sent at the 9th clock bit. reset clears this bit. 1 = ddc does not send acknowl edge signals at 9th clock bit 0 = ddc sends ac knowledge signal at 9th clock bit address: $0018 bit 7654321bit 0 read: den dien 00 txak sclien ddc1en 0 write: reset:00000000 = unimplemented figure 15-4. ddc cont rol register (dcr)
ddc12ab interface ddc registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor ddc12ab interface 201 sclien ? scl interrupt enable when this bit is set, the sclif flag is enabled to generate an interrupt request to the cpu. when sclien is cleared, sclif is prevented from generating an interrupt request. reset clears this bit. 1 = sclif bit set will genera te interrupt request to cpu 0 = sclif bit set wi ll not generate interr upt request to cpu ddc1en ? ddc1 pr otocol enable this bit is set to ena ble ddc1 protocol. the ddc 1 protocol will use the vsync input (from sync processor) as the master clock input to the ddc module. vsync risi ng-edge will c ontinuously clock out the data to the output circuit. no calli ng address comparison is performed. the srw bit in ddc status register (dsr) will always read as "1". reset clears this bit. 1 = ddc1 protocol enabled 0 = ddc1 protocol disabled 15.6.4 ddc master control register (dmcr) alif ? ddc arbitratio n lost interrupt flag this flag is set when software atte mpt to set mast but the bb has been set by detecting the st art condition on the lines or when the ddc is transmitting a "1" to sda line but detected a "0" from sda line in master mode ? an ar bitration loss. this bi t generates an interrupt request to the cpu if the dien bit in dcr is also set. this bit is cleared by writing "0" to it or by reset. 1 = lost arbitrati on in master mode 0 = no arbitration lost address: $0016 bit 7654321bit 0 read: alif nakif bb mast mrw br2 br1 br0 write: 00 reset:00000000 figure 15-5. ddc master control register (dmcr)
ddc12ab interface technical data mc68hc908ld60 ? rev. 1.1 202 ddc12ab interface freescale semiconductor nakif ? no acknowledge interrupt flag this flag is only set in master mo de (mast = 1) when there is no acknowledge bit detected after one data byte or calling address is transferred. this flag also clears mast. nakif generat es an interrupt request to cpu if t he dien bit in dcr is also set. this bit is cleared by writing "0" to it or by reset. 1 = no acknowl edge bit detected 0 = acknowledg e bit detected bb ? bus busy flag this flag is set after a start conditi on is detected (bus busy), and is cleared when a stop condition (bus idle) is detected or the ddc is disabled. reset clears this bit. 1 = start condition detected 0 = stop condition detect ed or ddc is disabled mast ? master control bit this bit is set to initia te a master mode transf er. in master mode, the module generates a star t condition to the sda and scl lines, followed by sending the calli ng address stored in dadr. when the mast bit is cleared by nakif set (no acknowledge) or by software, the module generat es the stop conditi on to the lines after the current byte is transmitted. if an arbitration loss occurs (alif = 1), the module reverts to slave mode by clearing mast, and releasing sda and scl lines immediately. this bit is cleared by writi ng "0" to it or by reset. 1 = master mode operation 0 = slave mode operation mrw ? master read/write this bit will be tr ansmitted out as bit 0 of th e calling address when the module sets the mast bit to enter master mode. the mrw bit determines the transfer direction of the data bytes that follows. when it is "1", the module is in master receive mode. when it is "0", the module is in master transmit mode. reset clears this bit. 1 = master mode receive 0 = master mode transmit
ddc12ab interface ddc registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor ddc12ab interface 203 br2?br0 ? baud rate select these three bits select one of eigh t clock rates as the master clock when the module is in master mode. since this master clock is deri ved the cpu bus cl ock, the user program should not execute the wait instruction when the ddc module in master mode. this will cause the sda and scl lines to hang, as the wait instru ction places the mcu in wait mode, with cpu clock is halted. these bits are cleared upon reset. (see table 15-2 . baud rate select .) table 15-2. baud rate select br2 br1 br0 baud rate 000 100k 001 50k 010 25k 011 12.5k 1 0 0 6.25k 1 0 1 3.125k 1 1 0 1.56k 1 1 1 0.78k note: cpu bus clock is external clock 4 = 6mhz
ddc12ab interface technical data mc68hc908ld60 ? rev. 1.1 204 ddc12ab interface freescale semiconductor 15.6.5 ddc status register (dsr) rxif ? ddc receive interrupt flag this flag is set after t he data receive register (ddrr) is loaded with a new received data. once the ddrr is loaded with received data, no more received data can be loaded to the ddrr register until the cpu reads the data from t he ddrr to clear rxbf fl ag. rxif generates an interrupt request to cpu if the dien bi t in dcr is also set. this bit is cleared by writing "0" to it or by reset; or when the den = 0. 1 = new data in data re ceive register (ddrr) 0 = no data received txif ? ddc transmit interrupt flag this flag is set when data in the data transmit register (ddtr) is downloaded to the output circuit, and that new data ca n be written to the ddtr. txif generates an interrup t request to cpu if the dien bit in dcr is also set. this bit is clea red by writing "0" to it or when the den = 0. 1 = data transfer completed 0 = data transfer in progress match ? ddc address match this flag is set when the received data in the data receive register (ddrr) is an calling address which ma tches with the address or its extended addresses (extad=1) specif ied in the d adr register. 1 = received address matches dadr 0 = received address does not match address: $0019 bit 7654321bit 0 read: rxif txif match srw rxak sclif txbe rxbf write: 0 0 0 reset:00001010 = unimplemented figure 15-6. ddc status register (dsr)
ddc12ab interface ddc registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor ddc12ab interface 205 srw ? ddc slav e read/write this bit indicates the data direction when the module is in slave mode. it is updated after t he calling address is rece ived from a master device. srw = 1 when the calling mast er is reading data from the module (slave transmit mode). srw = 0 when the master is writing data to the module (receive mode). 1 = slave mode transmit 0 = slave mode receive rxak ? ddc receive acknowledge when this bit is clear ed, it indicate s an acknowledge signal has been received after the comp letion of 8 data bits transmission on the bus. when rxak is set, it indicates no acknowledge signal has been detected at the 9th clo ck; the module will releas e the sda line for the master to generate "stop" or "repeated start" condi tion. reset sets this bit. 1 = no acknowledge signal received at 9th clock bit 0 = acknowledge signal re ceived at 9th clock bit sclif ? scl interrupt flag this flag is set when a falling edge is detected on the scl line, only if ddc1en bit is set. scli f generates an interrupt request to cpu if the sclien bit in dcr is al so set. sclif is cleared by writing "0" to it or when the dcc1en = 0, or den = 0. reset clears this bit. 1 = falling edge de tected on scl line 0 = no falling edge detected on scl line txbe ? ddc transmit buffer empty this flag indicates the status of th e data transmit r egister (ddtr). when the cpu writes the data to the ddtr, the t xbe flag will be cleared. txbe is set when ddtr is em ptied by a transf er of its data to the output circuit. reset sets this bit. 1 = data transmit register empty 0 = data transmit register full
ddc12ab interface technical data mc68hc908ld60 ? rev. 1.1 206 ddc12ab interface freescale semiconductor rxbf ? ddc rece ive buffer full this flag indicates the status of th e data receive register (ddrr). when the cpu reads the data from the ddrr, t he rxbf flag will be cleared. rxbf is set when ddrr is full by a transfer of data from the input circuit to the ddrr. reset clears this bit. 1 = data receive register full 0 = data receive register empty 15.6.6 ddc data transmit register (ddtr) when the ddc module is enabled, den = 1, data written into this register depends on whether module is in master or slave mode. in slave mode, the data in ddtr will be transferre d to the output circuit when: the module detects a matched ca lling address (match = 1), with the calling master re questing data (srw = 1); or the previous data in the output circuit has be tr ansmitted and the receiving master returns an a cknowledge bit, indicated by a received acknowledge bit (rxak = 0). if the calling master does not return an acknowledge bit (rxak = 1), the module will release the sda line for master to generate a "stop" or "repeated start" condition. the data in the ddtr will not be transferred to the output circuit until the nex t calling from a master. the transmit buffer empty flag remains cleared (txbe = 0). in master mode, the data in ddtr will be transfe rred to the output circuit when: address: $001a bit 7654321bit 0 read: dtd7 dtd6 dtd5 dtd4 dtd3 dtd2 dtd1 dtd0 write: reset:11111111 figure 15-7. ddc data tr ansmit register (ddtr)
ddc12ab interface ddc registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor ddc12ab interface 207 the module receives an ack nowledge bit (r xak = 0), after setting master transmit mode (m rw = 0), and the calling address has been transmitted; or the previous data in the output circuit has be tr ansmitted and the receiving slave retu rns an acknowledge bi t, indicated by a received acknowledge bit (rxak = 0). if the slave does not return an a cknowledge bit (rxak = 1), the master will generate a "stop" or "repeated start" condition. the data in the ddtr will not be transferred to the output circuit. the transmit buffer empty flag remains cleared (txbe = 0). the sequence of events for slave tr ansmit and master transmit are illustrated in figure 15-9 . 15.6.7 ddc data receive register (ddrr) when the ddc module is enabled, den = 1, data in this read-only register depends on whether module is in master or slave mode. in slave mode, the data in ddrr is: the calling address from the ma ster when the address match flag is set (match = 1); or the last data received when match = 0. in master mode, the data in the ddrr is: the last data received. address: $001b bit 7654321bit 0 read: drd7 drd6 drd5 dr d4 drd3 drd2 drd1 drd0 write: reset:00000000 = unimplemented figure 15-8. ddc data re ceive register (ddrr)
ddc12ab interface technical data mc68hc908ld60 ? rev. 1.1 208 ddc12ab interface freescale semiconductor when the ddrr is read by the cpu, the receive buf fer full flag is cleared (rxbf = 0), and the next received data is loade d to the ddrr. each time when new data is loaded to the d drr, the rxif interrupt flag is set, indicating that new data is available in ddrr. the sequence of events for slave receive and master receive are illustrated in figure 15-9 . 15.7 programming considerations when the ddc module detect s an arbitration loss in master mode, it will release both sda and scl lines immediately. but if there are no further stop conditions detected, the module will hang up. therefore, it is recommended to have time -out software to re cover from such ill condition. the software can start the ti me-out counter by looking at the bb (bus busy) flag in th e dmcr and reset the c ounter on the completion of one byte transmission. if a time-out occur, software can clear the den bit (disable ddc module) to releas e the bus, and hence clearing the bb flag. this is the only way to clear the bb flag by software if the module hangs up due to a no stop condition received. the ddc can resume operation again by se tting the den bit.
ddc12ab interface programming considerations mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor ddc12ab interface 209 figure 15-9. data transf er sequences for master/sla ve transmit/receive modes start address ack tx data1 txbe=0 mrw=0 mast=1 txif=1 txbe=1 nakif=1 mast=0 txbe=1 (a) master transmit mode (b) master receive mode (c) slave transmit mode txif=1 txbe=0 ack tx datan nak stop txif=1 txbe=1 start address ack rx data1 rxbf=0 mast=1 txbe=0 rxbf=1 rxif=1 nakif=1 mast=0 rxif=1 rxbf=1 ack rx datan nak stop 1 start address ack tx data1 txbe=1 rxbf=0 nakif=1 txbe=0 txbe=1 (d) slave receive mode txif=1 ack tx datan nak stop rxbf=1 rxif=1 match=1 srw=1 txif=1 txbe=1 0 start address ack rx data1 rxbf=1 rxif=1 rxif=1 rxbf=1 ack rx datan nak stop txbe=0 rxbf=0 rxbf=1 rxif=1 match=1 srw=0 data1 ddrr datan ddrr data1 ddtr data2 ddtr datan+2 ddtr data1 ddtr data2 ddtr data3 ddtr datan+2 ddtr (dummy data ddtr) mrw=1 data1 ddrr datan ddrr 0 1 key: shaded data packets indicate a transmit by the mcu?s ddc module
ddc12ab interface technical data mc68hc908ld60 ? rev. 1.1 210 ddc12ab interface freescale semiconductor
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor sync processor 211 technical data ? mc68hc908ld60 section 16. sync processor 16.1 contents 16.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 16.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 16.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 16.5 functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 16.5.1 polarity detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 16.5.1.1 hsync polarity detect ion . . . . . . . . . . . . . . . . . . . . . . . . 216 16.5.1.2 vsync polarity detect ion . . . . . . . . . . . . . . . . . . . . . . . . 216 16.5.1.3 composite sync polarity detect ion . . . . . . . . . . . . . . . . 216 16.5.2 sync signal counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 16.5.3 polarity controlled hout and vout outputs . . . . . . . . . . 217 16.5.4 clamp pulse output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 16.5.5 low vertical frequency detect . . . . . . . . . . . . . . . . . . . . . 219 16.6 sync processor i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . 219 16.6.1 sync processor control & stat us register ( spcsr). . . . . 219 16.6.2 sync processor input/output control register (spiocr) . 221 16.6.3 vertical frequency registers (vfrs) . . . . . . . . . . . . . . . . . 223 16.6.4 hsync frequency registers (hfrs). . . . . . . . . . . . . . . . . . 225 16.6.5 sync processor control register 1 (spcr1). . . . . . . . . . . 227 16.6.6 h & v sync output control re gister (hvocr) . . . . . . . . . 228 16.7 system operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
sync processor technical data mc68hc908ld60 ? rev. 1.1 212 sync processor frees cale semiconductor 16.2 introduction the sync processor is designed to detect and process sync signals inside a digital monitor system ? from separated hsync and vsync inputs. after detection and the necessary polarity correction and/or sync separation, the correct ed sync signals are sent out. the mcu can also send commands to other m onitor circuitry, such as for the geometry correction and osd, using the ddc12a b and/or the iic communication channels. the block diagram of the sync processor is shown in figure 16-2 . note: all quoted timings in this section assume an internal bus frequency of 6mhz. 16.3 features features of the sync proc essor include the following: polarity detector horizontal frequency counter vertical frequency counter low vertical frequency indicator (40.7hz) polarity controlled hout and vout outputs: ? from separate hsync and vsync ? from composite syn c on hsync input pin ? from internal selectable fr ee running hsync and vsync pulses free-running hsync, vsync, de, and dclk of 4 video modes clamp pulse output to the external pre-amp chip internal schmitt trigger on hsync, and vsync input pins to improve noise immunity
sync processor i/o pins mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor sync processor 213 16.4 i/o pins the sync processor uses seven i/o pins, with four pins shared with standard port i/o pins and one pin shar ed with timer channel 0. the full name of the sync processor i/o pins are listed in table 16-1 . the generic pin name appear in t he text that follows. table 16-1. pin name conventions sync processor generic pin names: full mcu pin names: pin selected for sync processor function by: hsync hsync ? vsync vsync ? hout ptd3/hout houte bit in pdcr ($0069) vout ptd2/vout voute bit in pdcr ($0069) de ptd1/de dee bit in pdcr ($0069) dclk ptd0/dclk dclke bit in pdcr ($0069) clamp clamp/tch0 els0b and els0a bits in tsc0 ($0010)
sync processor technical data mc68hc908ld60 ? rev. 1.1 214 sync processor frees cale semiconductor addr.register name bit 7654321bit 0 $0040 sync processor control and status register (spcsr) read: vsie vedge vsif comp vinvo hinvo vpol hpol write: 0 reset:00000000 $0041 vertical frequency high register (vfhr) read: vof 0 0 vf12 vf11 vf10 vf9 vf8 write: cpw1 cpw0 reset:00000000 $0042 vertical frequency low register (vflr) read: vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 write: reset:00000000 $0043 hsync frequency high register (hfhr) read: hfh7 hfh6 hfh5 hf h4 hfh3 hfh2 hfh1 hfh0 write: reset:00000000 $0044 hsync frequency low register (hflr) read: hover 0 0 hfl4 hfl3 hfl2 hfl1 hfl0 write: reset:00000000 $0045 sync processor i/o control register (spiocr) read: vsyncs hsyncs coinvrrrbporsout write: reset:000 00 $0046 sync processor control register 1 (spcr1) read: lvsie lvsif hps1 hps0 r r atpol fshf write: 0 reset:0000 00 $003f h&v sync output control register (hvocr) read: dclkph1 dclkph0 r hvocr1 hvocr0 write: reset: 00 00 = unimplemented r = reserved figure 16-1. sync processor i/o register summary
sync processor functional blocks mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor sync processor 215 16.5 functional blocks figure 16-2. sync pr ocessor block diagram 13-bit counter 48 a 1 b s extracted vsync a 1 b s svf comp sout vinvo vout polarity detect edge detect vpol one shot vedge internal bus clock overflow detect vof lvsie to interrupt logic 12-bit counter one shot overflow detect clk32/32.768 hsync dclk a 1 b s polarity detect hpol comp vsync extractor extracted vsync b a 1 s h/v sync, de, dclk dclk1 pulse generator svf shf clamp pulse generator clamp hout vflr vfhr hflr hfhr bpor coinv sout hover vpol vsie vsif $c00 detect lvsif hinvo hvocr[1:0] vsync 125khz 6mhz de from cgm dclkph[1:0]
sync processor technical data mc68hc908ld60 ? rev. 1.1 216 sync processor frees cale semiconductor 16.5.1 polarity detection 16.5.1.1 hsync polarity detection the hsync polarity detection circuit measures the length of high and low period of the hsync input. if the length of high is longer than l and the length of low is shorter than s , the hpol bit will be "0", indicating a negative polarity hsync in put. if the length of low is longer than l and the length of high is shorter than s , the hpol bit will be "1", indicating a positive polarity hsync input. the table below shows three possible cases for hsync polarity detection ? the conditions are selected by the hps[1:0] bits in the sync proc essor control register 1 (spcr1). 16.5.1.2 vsync polarity detection the vsync polarity detection circuit per forms a similar function as for hsync. if the length of high is l onger than 4ms and the length of low is shorter than 2ms, the vpol bit will be "0", indicating a negative polarity vsync input. if the length of low is longer t han 4ms and t he length of high is shorter than 2ms, the vpol bi t will be "1", indi cating a positive polarity vsync input. 16.5.1.3 composite sy nc polarity detection when a composite sync signal is t he input (comp = 1 for composite sync processing), the hpol bit = vpol bit, and the pol arity is detected using the vsync polarity detection criteria described in section 16.5.1.2 . polarity detection pulse width spcr1 ($0046) long is greater than ( l ) short is less than ( s ) hps1 hps0 7 s6 s00 3.5 s3 s1x 14 s12 s01
sync processor functional blocks mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor sync processor 217 16.5.2 sync signal counters there are two counters: a 13-bit horiz ontal frequency counter to count the number of horizontal sync pulses within a 32ms or 8ms period; and a 13-bit vertical frequency counter to count the number of system clock cycles between two vertical sync pulse s. these two dat a can be read by the cpu to che ck the signal frequencies and to determine the video mode. the 13-bit vertical frequency register encompasses vertical frequency range from approximately 15hz to 128khz. due to the asynchronous timing between the incomi ng vsync signal and intern al system clock, there will be 1 count er ror on reading the vert ical frequency registers (vfrs) for the same vertical frequency. the horizontal counter counts the pul ses on hsync pin input, and is uploaded to the hsync fr equency registers (hfrs) every 32.768ms or 8.192ms. 16.5.3 polarity controlled hout and vout outputs the processed sync signals are ou tput on hout an d vout when the corresponding bits in configuratio n register 0 ($0069) are set. the signal to these output pins depe nd on sout and comp bits (see table 16-2 ), with polarity contro lled by atpol, hinvo , and vinvo bits as shown in table 16-3 . table 16-2. sync output control sout comp sync outputs: vout and hout 1 x free-running video mode output 00 sync outputs follow sync inputs vsync and hsync respectively, with polarity correction shown in table 16-3 . 01 hout follows the composite sy nc input and vout is the extracted vsync (3 to 14 s delay to composite input), with polarity correction shown in table 16-3 .
sync processor technical data mc68hc908ld60 ? rev. 1.1 218 sync processor frees cale semiconductor when the sout bit is set, the hout output is a free-runn ing pulse. both hout and vout outputs are negativ e polarity, with frequencies selected by the h & v sync out put control regi ster (hvocr). 16.5.4 clamp pulse output when the els0b and els0a bits in t he tsc0 register are logic 0 (see table 11-3 ), a clamp signal is output on the clam p pin. this clamp pulse is triggered either on the leading edge or the trailing edge of hsync, controlled by bpor bit, wit h the polarity c ontrolled by the coinv bit. see figure 16-3 . clamp pulse output timing . figure 16-3. clamp pulse output timing table 16-3. sync output polarity atpol sout vinvo or hinvo sync outputs: vout/hout x 1 x free-running video mode output 0 0 0 same polarity as sync input 0 0 1 inverted polarity of sync input 1 0 0 negative polarity sync output 1 0 1 positive polarity sync output pulse width = 0.33~2.1 s pulse width = 0.33~2.1 s pulse width = 0.33~2.1 s pulse width = 0.33~2.1 s hsync (hpol = 1) clamp (bpor = 0) clamp (bpor = 1) hsync (hpol = 0) clamp (bpor = 0) clamp (bpor = 1)
sync processor sync processor i/o registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor sync processor 219 16.5.5 low vertical frequency detect logic monitors the value of the vsync frequency register (vfr), and sets the low vertical frequency flag (l vsif) when the value of vfr is higher than $c00 (frequency below 40.7hz). lvsif bit can generate an interrupt request to t he cpu when the lvsie bit is set and i-bit in the condition code re gister is "0". the lvsif bit can help the system to detect video off mode fast. 16.6 sync process or i/o registers eight registers are associ ated with the sync proce ssor, they outlined in the following sections. 16.6.1 sync processor control & status register (spcsr) vsie ? vsync interrupt enable when this bit is set, the vsif flag is enabled to generate an interrupt request to the cpu. when vsie is cleared, the vsif flag is prevented from generating an interrupt request to the cpu. reset clears this bit. 1 = vsif bit set will generat e interrupt request to cpu 0 = vsif bit set does not generate interr upt request to cpu address: $0040 bit 7654321bit 0 read: vsie vedge vsif comp vinvo hinvo vpol hpol write: 0 reset:00000000 = unimplemented figure 16-4. sync processor cont rol & status register (spcsr)
sync processor technical data mc68hc908ld60 ? rev. 1.1 220 sync processor frees cale semiconductor vedge ? vsync interrupt edge select this bit specifies the triggering edge of vsync interrupt. when it is "0", the rising edge of internal vsync signal which is either from the vsync pin or extracted from the composite input signal will set vsif flag. when it is "1", t he falling edge of internal vsync signal will set vsif flag. reset clears this bit. 1 = vsif bit will be set by rising edge of vsync 0 = vsif bit will be set by falling edge of vsync vsif ? vsync interrupt flag this flag is only set by the specified edge of the internal vsync signal, which is either from the vsync input pin or extracted from the composite sync input si gnal. the triggering edge is specified by the vedge bit. vsif generat es an interrupt reques t to the cpu if the vsie bit is also set. this bit is cleared by writing a "0" to it or by a reset. 1 = a valid edge is detected on the vsync 0 = no valid vsync is detected comp ? composite sync input enable this bit is set to enable the separato r circuit which extracts the vsync pulse from the composite sync input on hsync or sog pin (select by sogsel bit). the extracted vsync signa l is used as it were from the vsync input. reset clears this bit. 1 = composite sync input enabled 0 = composite sync input disabled vinvo ? vout signal polarity this bit, toget her with the atpol bit in spcr1 controls the output polarity of the vout signal (see table 16-4 ). hinvo ? hout signal polarity this bit, toget her with the atpol bit in spcr1 controls the output polarity of the hout signal (see table 16-4 ).
sync processor sync processor i/o registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor sync processor 221 vpol ? vsync input polarity this bit indicates the polarity of the vsync input, or t he extracted vsync from a composite sync input (comp=1). reset clears this bit. 1 = vsync is positive polarity 0 = vsync is negative polarity hpol ? hsync input polarity this bit indicates the polarity of the hsync input. thi s bit equals the vpol bit when the co mp bit is set. re set clears this bit. 1 = hsync is positive polarity 0 = hsync is negative polarity 16.6.2 sync processor input/output control register (spiocr) vsyncs ? vsync input state this read-only bit reflects the l ogical state of the vsync input. hsyncs ? hsync input state this read-only bit reflects the l ogical state of the hsync input. table 16-4. atpol, vinvo, and hinvo setting atpol vinvo / hinvo sync outputs: vout/hout 0 0 same polarity as sync input 0 1 inverted polarity of sync input 1 0 negative polarity sync output 1 1 positive polarity sync output address: $0045 bit 7654321bit 0 read: vsyncs hsyncs coinvrrrbporsout write: reset:000 00 = unimplemented r = reserved figure 16-5. sync processor input/output contro l register (spiocr)
sync processor technical data mc68hc908ld60 ? rev. 1.1 222 sync processor frees cale semiconductor coinv ? clamp output invert this bit is set to inve rt the clamp pulse out put to negative. reset clears this bit. 1 = clamp output is se t for negative pulses 0 = clamp output is se t for positive pulses bpor ? back porch this bit defines the tri ggering edge of the clamp pu lse output relative to the hsync input. reset clears this bit. 1 = clamp pulse is generated on the trailing edge of hsync 0 = clamp pulse is generated on the leading edge of hsync sout ? sync output enable this bit will select the output signals for the vout and hout pins and generate the de and dclk signals to the pins . reset clears this bit. 1 = vout, hout, de, and dclk ou tputs are internally generated free-running timing pulses with frequenc ies determined by hvcor[1:0] bits in hvcor and cgm values. 0 = vout and hout outputs are processed vsync and hsync inputs respectively and de and dclk are hold as logic low.
sync processor sync processor i/o registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor sync processor 223 16.6.3 vertical frequency registers (vfrs) this register pair c ontains the 13-bit vertical frequency count value, an overflow bit, and the clamp pulse width selection bits. vf[12:0] ? vertical frame frequency this read-only 13-bit contains info rmation of the vertical frame frequency. an internal 13-bit counter counts the number of 8 s periods between two vsync pulses. the most significant 5 bits of the counted value is transferred to the hi gh byte register, and the least significant 8 bits is transferred to an interm ediate buffer. when the high byte register is read, the 8-bit counted val ue stored in the intermediate buffer will be uploaded to the lo w byte register. therefore, user program must read t he high byte register first, then low byte register in order to get the comple te counted value of one vertical frame. if the counter overfl ows, the overflow flag, vof, will be set, indicating the counter value st ored in the vfrs is meaningless. the data corresponds to th e period of one vertical frame. this register can be read to determine if t he frame frequency is valid, and to determine the video mode. address: $0041 bit 7654321bit 0 read: vof 0 0 vf12 vf11 vf10 vf9 vf8 write: cpw1 cpw0 reset:00000000 figure 16-6. vertical frequency high register address: $0042 bit 7654321bit 0 read: vf7 vf6 vf5 vf4 vf3 vf2 vf1 vf0 write: reset:00000000 = unimplemented figure 16-7. vertical frequency low register
sync processor technical data mc68hc908ld60 ? rev. 1.1 224 sync processor frees cale semiconductor the frame frequency is calculated by: table 16-5 shows examples for the vert ical frequency regi ster, all vfr numbers are in hexadecimal. vof ? vertical frequen cy counter overflow this read-only bit is set when an over flow has occurred on the 13-bit vertical frequency counter. reset clears this bit, and will be updated every vertical frame. an overflow occurs when the period of vsync frame exceeds 64.768ms (a vertical frame fr equency lower than 15.258hz). 1 = a vertical frequency count er overflow has occurred 0 = no vertical frequency counter overflow has occurred table 16-5. sample ve rtical frame frequencies vfr max freq. min freq. vfr max freq. min freq. $02a0 186.20 hz 185.70 hz $0780 65.10 hz 65.00 hz $03c0 130.34 hz 130.07 hz $0823 60.04 hz 59.98 hz $03c1 130.21 hz 129.94 hz $0824 60.01 hz 59.95 hz $03c2 130.07 hz 129.80 hz $0825 59.98 hz 59.92 hz $04e2 100.08 hz 99.92 hz $09c4 50.02 hz 49.98 hz $04e3 100.00 hz 99.84 hz $09c5 50.00 hz 49.96 hz $04e4 99.92 hz 99.76 hz $09c6 49.98 hz 49.94 hz $06f9 70.07 hz 69.99 hz $1ffd 15.266 hz 15.262 hz $06fa 70.03 hz 69.95 hz $1ffe 15.264 hz 15.260 hz $06fb 69.99 hz 69.91 hz $1fff 15.262 hz 15.258 hz vertical frame frequency 1 vfr 1 48 t cyc --------------- ----------------- ------------------ - = 1 vfr 1 8 s ------------------ ------------------- - = for internal bus clock of 6mhz
sync processor sync processor i/o registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor sync processor 225 cpw[1:0] ? clamp pulse width the cpw1 and cpw0 bits are used to select the output clamp pulse width. reset clears these bits, se lecting a default clamp pulse width between 0.33 s and 0.375 s. these bits al ways read as zeros. 16.6.4 hsync frequency registers (hfrs) this register pair contains the 13-bit hsyn c frequency count value and an overflow bit. table 16-6. clamp pulse width cpw1 cpw0 clamp pulse width 0 0 0.33 s to 0.375 s 010.5 s to 0.542 s 1 0 0.75 s to 0.792 s 112 s to 2.042 s address: $0043 bit 7654321bit 0 read: hfh7 hfh6 hfh5 hf h4 hfh3 hfh2 hfh1 hfh0 write: reset:00000000 figure 16-8. hsync fr equency high register address: $0044 bit 7654321bit 0 read: hover 0 0 hfl4 hfl3 hfl2 hfl1 hfl0 write: reset:00000000 = unimplemented figure 16-9. hsync frequency low register
sync processor technical data mc68hc908ld60 ? rev. 1.1 226 sync processor frees cale semiconductor hfh[7:0], hfl[4:0] ? ho rizontal line frequency this read-only 13-bit cont ains the number of ho rizontal lines in a 32ms window. an internal 13-bit counter counts the hsync pulses within a 32ms window in every 32.7 68ms period. if the fshf bit in spcr1 is set, only the most 11-bi ts (hfh[7:0] & hfl[4:2]) will be updated by the counter. thus, providi ng a hsync pulse count in a 8ms window in every 8.192ms. the most significant 8 bits of counted value is tr ansferred to the high byte register, and the l east significant 5 bits is transferred to an intermediate buffer. when the high byte regist er is read, the 5-bit counted value stored in the interm ediate buffer will be uploaded to the low byte register. therefore, user the program must read the high byte register first then low byte regist er in order to get the complete counted value of hsync pulses. if t he counter overflows, the overflow flag, hover, will be set, indicating the num ber of hsync pulses in 32ms are more than 8191 (2 13 ?1), i.e. a hsync frequency greater than 256khz. for the 32ms window, the hfhr and hflr are such that the frequency step unit in the 5-bit of hflr is 0.03125khz, and the step unit in the 8-bit hfhr is 1khz. therefore, the hsync frequency can be easily calculated by: hover ? hsync frequen cy counter overflow this read-only bit is set when an over flow has occurred on the 13-bit hsync frequency counter. reset clear s this bit, and will be updated every count period. an overflow occurs when the num ber hsync pulses exceed 8191, a hsync frequency great er than 256khz. 1 = a hsync frequency counter overflow has occurred 0 = no hsync frequency coun ter overflow has occurred hsync frequency = [ hfh + ( hfl 0.03125)] khz where: hfh is the value of hfh[7:0] hfl is the value of hfl[4:0]
sync processor sync processor i/o registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor sync processor 227 16.6.5 sync processor control register 1 (spcr1) lvsie ? low vsync interrupt enable when this bit is set, the lvsif fl ag is enabled to generate an interrupt request to the cpu. w hen lvsie is cleared, the lvsif flag is prevented from generating an interrupt request to the cpu. reset clears this bit. 1 = low vsync interrupt enabled 0 = low vsync interrupt disabled lvsif ? low vsync interrupt flag this read-only bit is set when the va lue of vfr is higher than $c00 (vertical frame frequency below 40.7hz). lvsif generates an interrupt request to the cpu if the lvsi e is also set. this bit is cleared by writing a "0" to it or reset. 1 = vertical frequency is below 40.7hz 0 = vertical frequency is higher than 40.7hz hps[1:0] ? hsync input detecti on pulse width these two bits control the detecti on pulse width of hsync input. reset clears these two bits, sett ing a default middle frequency of hsync input. address: $0046 bit 7654321bit 0 read: lvsie lvsif hps1 hps0 r r atpol fshf write: 0 reset:0000 00 = unimplemented r = reserved figure 16-10. sync processor cont rol register 1 (spcr1) table 16-7. hsync polarity detection pulse width hps1 hps0 polarity detection pulse width 0 0 long > 7 s and short < 6 s 1 x long > 3.5 s and short < 3 s 0 1 long > 14 s and short < 12 s
sync processor technical data mc68hc908ld60 ? rev. 1.1 228 sync processor frees cale semiconductor atpol ? auto polarity this bit, toget her with the vinvo or hinvo bits in spcsr controls the output polarity of t he vout or hout signals respectively. reset clears this bit (see table 16-8 ). fshf ? fast horizontal frequency count this bit is set to s horten the measurement cycle of the horizontal frequency. if it is set, only hfh[7:0] and hfl[4:2] will be updated by the hsync counter, pr oviding a count in a 8ms window in every 8.192ms, with hfl[1:0] reading as zeros. therefore, user can determine the horizontal frequency c hange within 8.192ms to protect critical circuitry. re set clears this bit. 1 = number of hsync pulse s is counted in an 8ms window 0 = number of hsync pulses is counted in a 32ms window 16.6.6 h & v sync output control register (hvocr) table 16-8. atpol, vinvo, and hinvo setting atpol vinvo / hinvo sync outputs: vout/hout 0 0 same polarity as sync input 0 1 inverted polarity of sync input 1 0 negative polarity sync output 1 1 positive polarity sync output address: $003f bit 7654321bit 0 read: dclkph1 dclkph0 r hvocr1 hvocr0 write: reset: 00 00 = unimplemented r = reserved figure 16-11. h&v sy nc output control register (hvocr)
sync processor system operation mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor sync processor 229 dclkph[1:0] ? dclk output phase adjustment these two bits are programmed to adjust the dclk output phase. each increment adds app roximately 2 to 3ns delay to the dclk output. hvocr[1:0] ? free runni ng video mode select bits these two bits together with mul[ 7:4] and vrs[7:4] in cgm?s pll programming register determine the frequencies of the internal generated free-running si gnals for output to hout, vout, de, and dclk pins, when the sout bit is set in the syn c processor i/o control register. these two bits determine the presca ler of pll reference clock in the cgm module. when hvoc r[1:0]=11, the prescaler is 2; for other values, t he prescaler is 3. reset clears these bits, setting a default horizontal frequency of 31.25khz and a ve rtical frequency of 60hz, a video mode of 640 480. (see section 8. cl ock generator module (cgm) .) 16.7 system operation this sync processor is designed to a ssist in determining the video mode of incoming hsync and vsy nc of various frequenc ies and polarities, and dpms modes. in the dpms standard, a no sync pulses definition can be detected when the value of the hsync frequency register (the number of hsync pulses) is less than one or when the vof bit is set. since the hsync frequency register is updated repeatedly in every 32.768ms, and a valid vsync must have a frequen cy greater than 40.7hz, a valid vsync pul se will arrive withi n the 32.768ms window. therefore, the user should read t he hsync frequency register every 32.768ms to determine the presence of hsync and/or vsync pulses. table 16-9. free-runn ing hsout, vsout, de, and dclk settings hvocr[1:0] mul[7:4] vrs[7:4] hout frequency vout frequency dclk frequency de video mode 00 3 3 31.45khz 59.91hz 24mhz vga 640 480 01 5 3 37.87khz 60.31hz 40mhz svga 800 600 10 8 6 48.37khz 60.31hz 64mhz xga 1024 768 11 9 9 64.32khz 60.00hz 108mhz sxga 1280 1024
sync processor technical data mc68hc908ld60 ? rev. 1.1 230 sync processor frees cale semiconductor
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 231 technical data ? mc68hc908ld60 section 17. input/output (i/o) ports 17.1 contents 17.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 17.3 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 17.3.1 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 17.3.2 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . 236 17.3.3 port a options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 17.4 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 17.4.1 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 17.4.2 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . 239 17.4.3 port b options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 17.5 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 17.5.1 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 17.5.2 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . 242 17.5.3 port c options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 17.6 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 17.6.1 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 17.6.2 data direction register d. . . . . . . . . . . . . . . . . . . . . . . . . . 245 17.6.3 port d options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 17.7 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 17.7.1 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 17.7.2 data direction register e. . . . . . . . . . . . . . . . . . . . . . . . . . 249
input/output (i/o) ports technical data mc68hc908ld60 ? rev. 1.1 232 input/output (i/o) ports freescale semiconductor 17.2 introduction thirty-nine (39) bidirecti onal input-output (i/o) pins form five parallel ports. all i/o pins are progr ammable as inputs or outputs. note: connect any unused i/o pins to an appr opriate logic level, either v dd or v ss . although the i/o ports do not require te rmination for proper operation, termination reduces e xcess current consumption and the possibility of el ectrostatic damage. addr.register name bit 7654321bit 0 $0000 port a data register (pta) read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset $0001 port b data register (ptb) read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset $0002 port c data register (ptc) read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset $0003 port d data register (ptd) read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 = unimplemented figure 17-1. port i/o register summary
input/output (i/o) ports introduction mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 233 $0006 data direction register c (ddrc) read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 $0007 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 $0008 port e data register (pte) read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset $0009 data direction register e (ddre) read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 $004f keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 $0069 port-d control register (pdcr) read: iicdate iicscle ddcdate ddcscle houte voute dee dclke write: reset:00000000 $0078 pwm control register (pwmcr) read: pwm7e pwm6e pwm5e pwm4e pwm3e pwm2e pwm1e pwm0e write: reset:00000000 addr.register name bit 7654321bit 0 = unimplemented figure 17-1. port i/o re gister summary (continued)
input/output (i/o) ports technical data mc68hc908ld60 ? rev. 1.1 234 input/output (i/o) ports freescale semiconductor table 17-1. port contro l register bits summary port bit ddr module control pin module register control bit a 0 ddra0 kbi kbier $004f kbie0 pta0/kbi0 1 ddra1 kbie1 pta1/kbi1 2 ddra2 kbie2 pta2/kbi2 3 ddra3 kbie3 pta3/kbi3 4 ddra4 kbie4 pta4/kbi4 5 ddra5 kbie5 pta5/kbi5 6 ddra6 kbie6 pta6/kbi6 7 ddra7 kbie7 pta7/kbi7 b 0 ddrb0 pwm pwmcr $0078 pwm0e ptb0/pwm0 1 ddrb1 pwm1e ptb1/pwm1 2 ddrb2 pwm2e ptb2/pwm2 3 ddrb3 pwm3e ptb3/pwm3 4 ddrb4 pwm4e ptb4/pwm4 5 ddrb5 pwm5e ptb5/pwm5 6 ddrb6 pwm6e ptb6/pwm6 7 ddrb7 pwm7e ptb7/pwm7 c 0 ddrc0 adc adscr $003b adch[4:0] ptc0/adc0 1 ddrc1 ptc1/adc1 2 ddrc2 ptc2/adc2 3 ddrc3 ptc3/adc3 4 ddrc4 ptc4/adc4 5 ddrc5 ptc5/adc5 6 ddrc6 ?? ?ptc6 d 0 ddrd0 sync pdcr $0069 dclke ptd0/dclk 1 ddrd1 dee ptd1/de 2 ddrd2 voute ptd2/vout 3 ddrd3 houte ptd3/hout 4 ddrd4 ddc12ab ddcscle ptd4/ddcscl 5 ddrd5 ddcdate ptd5/ddcsda 6 ddrd6 mmiic iicscle ptd6/iicscl 7 ddrd7 iicdate ptd7/iicsda e 0 ddre0 ??? pte0 1 ddre1 pte1 2 ddre2 pte2 3 ddre3 pte3 4 ddre4 pte4 5 ddre5 pte5 6 ddre6 pte6 7 ddre7 pte7
input/output (i/o) ports port a mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 235 17.3 port a port a is an 8-bit special- function port that shares all eight of its pins with the keyboard interrupt module (kbi). (see section 19. keyboard interrupt module (kbi) .) 17.3.1 port a data register the port a data register (p ta) contains a data latch for each of the eight port a pins. pta[7:0] ? port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. kbi[7:0] ? keyboard interrupt pins the keyboard interrupt enable bits , kbie[7:0], in the keyboard interrupt enable register (kbier), enable the port a pins as external interrupt pins. (see 17.3.3 port a options and section 19. keyboard interrupt module (kbi) .) address: $0000 bit 7654321bit 0 read: pta7 pta6 pta5 pta4 pta3 pta2 pta1 pta0 write: reset: unaffected by reset alternative function: kbi7 kbi6 kbi5 kbi4 kbi3 kbi2 kbi1 kbi0 figure 17-2. port a data register (pta)
input/output (i/o) ports technical data mc68hc908ld60 ? rev. 1.1 236 input/output (i/o) ports freescale semiconductor 17.3.2 data direction register a data direction register a (ddra) dete rmines whether each port a pin is an input or an output. wr iting a logic 1 to a d dra bit enables the output buffer for the corresponding port a pi n; a logic 0 dis ables the output buffer. ddra[7:0] ? data dire ction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pi ns by writing to the port a data register before changing data direction regist er a bits fr om 0 to 1. figure 17-4 shows the port a i/o logic. figure 17-4. port a i/o circuit address: $0004 bit 7654321bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset:00000000 figure 17-3. data dir ection register a (ddra) read ddra ($0004) write ddra ($0004) reset write pta ($0000) read pta ($0000) ptax ddrax ptax internal data bus
input/output (i/o) ports port a mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 237 when bit ddrax is a l ogic 1, reading address $0000 reads the ptax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-2 summarizes the operation of the port a pins. 17.3.3 port a options the keyboard interrupt enabl e register (kbier) se lects the port a pins for keyboard interrupt function or as standar d i/o function. (see section 19. keyboard interr upt module (kbi) .) kbie[7:0] ? keyboard interrupt enable bits setting a kbiex bit to logic 1 c onfigures the pt ax/kbix pin for keyboard interrupt function. reset clears the kbiex bits. 1 = ptax/kbix pin configur ed as kbix interrupt pin 0 = ptax/kbix pin configured as pt ax standard i/o pin table 17-2. port a pin functions ddra bit pta bit i/o pin mode accesses to ddra accesses to pta read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddra[7:0] pin pta[7:0] (3) 3. writing affects data regist er, but does not affect input. 1 x output ddra[7:0] pta[7:0] pta[7:0] address: $004f bit 7654321bit 0 read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 17-5. keyboard interr upt enable register (kier)
input/output (i/o) ports technical data mc68hc908ld60 ? rev. 1.1 238 input/output (i/o) ports freescale semiconductor 17.4 port b port b is an 8-bit special- function port that shares all eight of its pins with the pulse width modulator (pwm). (see section 12. pulse width modulator (pwm) .) 17.4.1 port b data register the port b data register (p tb) contains a data latch for each of the eight port pins. ptb[7:0] ? port b data bits these read/write bits are software-p rogrammable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. pwm[7:0] ? pwm outputs pins the pwm output enable bits pwm7e? pwm0e, in the pwm control register (pwmcr) enable port b pins as pwm output pins. (see 17.4.3 port b options and section 12. pulse width modulator (pwm) .) address: $0001 bit 7654321bit 0 read: ptb7 ptb6 ptb5 ptb4 ptb3 ptb2 ptb1 ptb0 write: reset: unaffected by reset alternative function: pwm7 pwm6 pwm5 pwm4 pwm3 pwm2 pwm1 pwm0 figure 17-6. port b data register (ptb)
input/output (i/o) ports port b mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 239 17.4.2 data direction register b data direction register b (ddrb) dete rmines whether each port b pin is an input or an output. wr iting a logic 1 to a d drb bit enables the output buffer for the corresponding port b pi n; a logic 0 dis ables the output buffer. ddrb[7:0] ? data dire ction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pi ns by writing to the port b data register before changing data direction regist er b bits fr om 0 to 1. figure 17-8 shows the port b i/o logic. figure 17-8. port b i/o circuit address: $0005 bit 7654321bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset:00000000 figure 17-7. data direct ion register b (ddrb) read ddrb ($0005) write ddrb ($0005) reset write ptb ($0001) read ptb ($0001) ptbx ddrbx ptbx internal data bus
input/output (i/o) ports technical data mc68hc908ld60 ? rev. 1.1 240 input/output (i/o) ports freescale semiconductor when bit ddrbx is a l ogic 1, reading address $0001 reads the ptbx data latch. when bit ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-3 summarizes the operation of the port b pins. 17.4.3 port b options the pwm control register (pwmcr) selects the port b pins for pwm function or as standard i/o function. (see section 12. pulse width modulator (pwm) .) pwm7e?pwm0e ? pwm output enable bits setting a pwmxe bit to logic 1 configures th e ptbx/pwmx pin for pwm output function. rese t clears the pwmxe bits. 1 = ptbax/pwmx pin configur ed as pwmx interrupt pin 0 = ptbax/pwmx pin configur ed as ptbx standard i/o pin table 17-3. port b pin functions ddrb bit ptb bit i/o pin mode accesses to ddrb accesses to ptb read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrb[6:0] pin ptb[6:0] (3) 3. writing affects data regist er, but does not affect input. 1 x output ddrb[6:0] ptb[6:0] ptb[6:0] address: $0078 bit 7654321bit 0 read: pwm7e pwm6e pwm5e pwm4e pwm3e pwm2e pwm1e pwm0e write: reset:00000000 figure 17-9. pwm cont rol register (pwmcr)
input/output (i/o) ports port c mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 241 17.5 port c port c is an 7-bit specia l-function port that shares six of its pins with the analog-to-digital converte r (adc) module. (see section 13. analog-to- digital converter (adc) .) 17.5.1 port c data register the port c data register (ptc) contains a data latch for each of the seven port c pins. ptc[6:0] ? port c data bits these read/write bits are software-p rogrammable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. adc[5:0] ? analog-to -digital input pins adc[5:0] are pins used for the i nput channels to the analog-to-digital converter module. the channel se lect bits, adch[4:0], in the adc status and control register define which port c pin will be used as an adc input and overrides any control from t he port i/o logic. (see 17.5.3 port c options and section 13. analog-to-digital converter (adc) .) address: $0002 bit 7654321bit 0 read: 0 ptc6 ptc5 ptc4 ptc3 ptc2 ptc1 ptc0 write: reset: unaffected by reset alternative function: adc5 adc4 adc3 adc2 adc1 adc0 = unimplemented figure 17-10. port c da ta register (ptc)
input/output (i/o) ports technical data mc68hc908ld60 ? rev. 1.1 242 input/output (i/o) ports freescale semiconductor note: care must be taken w hen reading port c while applying analog voltages to adc5?adc0 pins . if the appropriate adc channel is not enabled, excessive current drain may occur if analog voltages are applied to the ptcx/adcx pin, while ptc is read as a digital input. those ports not selected as analog input channels are considered digital i/o ports. 17.5.2 data direction register c data direction register c (ddrc) determines whet her each port c pin is an input or an output. writ ing a logic 1 to a dd rc bit enables the output buffer for the corresponding port c pi n; a logic 0 dis ables the output buffer. ddrc[6:0] ? data dire ction register c bits these read/write bits control port c data direction. reset clears ddrc[6:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writ ing to the port c dat a register before changing data direction regist er c bits fr om 0 to 1. figure 17-12 shows the port c i/o logic. address: $0006 bit 7654321bit 0 read: 0 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset:00000000 = unimplemented figure 17-11. data direct ion register c (ddrc)
input/output (i/o) ports port c mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 243 figure 17-12. port c i/o circuit when bit ddrcx is a l ogic 1, reading address $0002 reads the ptcx data latch. when bit ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-4 summarizes the operation of the port c pins. 17.5.3 port c options the adch[4:0] bits in the adc status and control register defines which ptcx/adcx pin is used as an adc input and overrides any control from the port i/o logic by forcing that pin as the input to the analog circuitry. (see section 13. analog-to- digital converter (adc) .) table 17-4. port c pin functions ddrc bit ptc bit i/o pin mode accesses to ddrc accesses to ptc read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrc[6:0] pin ptc[6:0] (3) 3. writing affects data regist er, but does not affect input. 1 x output ddrc[6:0] ptc[6:0] ptc[6:0] read ddrc ($0006) write ddrc ($0006) reset write ptc ($0002) read ptc ($0002) ptcx ddrcx ptcx internal data bus
input/output (i/o) ports technical data mc68hc908ld60 ? rev. 1.1 244 input/output (i/o) ports freescale semiconductor 17.6 port d port d is an 8-bit special-function port t hat shares two of its pins with the multi-master iic (mmiic ) module, two of its pins with the ddc12ab module, and four of its pins with the sync processor. 17.6.1 port d data register the port d data register (ptd) contains a data latch for each of the eight port d pins. ptd[7:0] ? port d data bits these read/write bits are software-p rogrammable. data direction of each port d pin is under the control of the corresponding bit in data direction register d. reset has no effect on port d data. iicsda, iicscl ? multi-mast er iic data and clock pins the ptd7/iicsda and ptd6/iicscl pi ns are multi-master iic data and clock pins. when the iicdate and iicscle bits in the port d control register (pdcr) ar e clear, the pt d7/iicsda and ptd6/iicscl pins are avail able for general-purpose i/o. (see 17.6.3 port d options .) ddcscl, ddcsda ? ddc12ab data and clock pins the ptd4/ddcscl and ptd5/ddcsda pins are ddc12ab clock and data pins respectively. when the ddcscle and ddcdate bits in the port d control register (pdcr) are clear, the ptd4/ddcscl and ptd5/ddcsda pins are available for general-purpose i/o. (see 17.6.3 port d options .) address: $0003 bit 7654321bit 0 read: ptd7 ptd6 ptd5 ptd4 ptd3 ptd2 ptd1 ptd0 write: reset: unaffected by reset alternative function: iicsda iicsc l ddcsda ddcscl hout vout de dclk figure 17-13. port d da ta register (ptd)
input/output (i/o) ports port d mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 245 hout? sync processor hout pulse output pin the ptd3/hout pin is t he sync processor hout pulse output pin. when the houte bit in the port d control register (pdcr) is clear, the ptd3/hout pin is available for general-purpo se i/o. (see 17.6.3 port d options .) vout ? sync processor vout pulse output pin the ptd2/vout pin is t he sync processor vout pulse output pin. when the voute bit in the port d cont rol register (pdcr) is clear, the ptd2/vout pin is available for general-purpos e i/o. (see 17.6.3 port d options .) de ? sync processor de pulse output pin the ptd1/de pin is the sync processo r de pulse output pin. when the dee bit in the port d control register (pdcr) is clear, the ptd1/de pin is available fo r general-purpose i/o. (see 17.6.3 port d options .) dclk ? sync processor dclk pulse output pin the ptd0/dclk pin is the sync proc essor dclk pulse output pin. when the dclke bit in the port d con trol register (pdcr) is clear, the ptd0/dclk pin is available for general-purpose i/o. (see 17.6.3 port d options .) 17.6.2 data direction register d data direction register d (ddrd) determines whet her each port d pin is an input or an output. writ ing a logic 1 to a dd rd bit enables the output buffer for the corresponding port d pi n; a logic 0 dis ables the output buffer. address: $0007 bit 7654321bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset:00000000 figure 17-14. data direct ion register d (ddrd)
input/output (i/o) ports technical data mc68hc908ld60 ? rev. 1.1 246 input/output (i/o) ports freescale semiconductor ddrd[7:0] ? data dire ction register d bits these read/write bits control port d data direction. reset clears ddrd[7:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note: avoid glitches on port d pins by writ ing to the port d dat a register before changing data direction regist er d bits fr om 0 to 1. figure 17-15 shows the port d i/o logic. figure 17-15. port d i/o circuit when bit ddrdx is a l ogic 1, reading address $0003 reads the ptdx data latch. when bit ddrdx is a logic 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-5 summarizes the operation of the port d pins. table 17-5. port d pin functions ddrd bit ptd bit i/o pin mode accesses to ddrd accesses to ptd read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddrd[7:0] pin ptd[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddrd[7:0] ptd[7:0] ptd[7:0] read ddrd ($0007) write ddrd ($0007) reset write ptd ($0003) read ptd ($0003) ptdx ddrdx ptdx internal data bus
input/output (i/o) ports port d mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 247 17.6.3 port d options the port d control register (pdcr) selects the po rt d pins for module function or as st andard i/o function. iicdate ? mmiic data pin enable this bit is set to conf igure the ptd7/iicsda pi n for iicsda function. reset clears this bit. 1 = ptd7/iicsda pin conf igured as iicsda pin 0 = ptd7/iicsda pin conf igured as standard i/o pin iicscle ? mmiic clock pin enable this bit is set to conf igure the ptd6/iicscl pi n for iicscl function. reset clears this bit. 1 = ptd6/iicscl pin conf igured as iicscl pin 0 = ptd6/iicscl pin conf igured as standard i/o pin ddcdate ? ddc data pin enable this bit is set to configure the ptd5/ ddcsda pin for ddcsda function. reset clears this bit. 1 = ptd5/ddcsda pin conf igured as ddcsda pin 0 = ptd5/ddcsda pin configur ed as standard i/o port ddcscle ? ddc clock pin enable this bit is set to c onfigure the ptd4/ddc scl pin for ddcscl function. reset clears this bit. 1 = ptd4/ddcscl pin configured as ddcscl pin 0 = ptd4/ddcscl pin confi gured as standard i/o port address: $0069 bit 7654321bit 0 read: iicdate iicscle ddcdate ddcscle houte voute dee dclke write: reset:00000000 figure 17-16. port d co ntrol register (pdcr)
input/output (i/o) ports technical data mc68hc908ld60 ? rev. 1.1 248 input/output (i/o) ports freescale semiconductor houte ? hout pin enable this bit is set to c onfigure the ptd3/hout pin for sync processor hout output. reset clears this bit. 1 = ptd3/hout pin conf igured as hout pin 0 = ptd3/hout pin confi gured as standard i/o pin voute ? vout pin enable this bit is set to c onfigure the ptd2/vout pin for sync processor vout output. reset clears this bit. 1 = ptd2/vout pin conf igured as vout pin 0 = ptd2/vout pin confi gured as standard i/o pin dee ? de pin enable this bit is set to conf igure the ptd1/de pin for sync processor de output. reset clears this bit. 1 = ptd1/de pin configured as de pin 0 = ptd1/de pin configur ed as standard i/o pin dclke ? dclk pin enable this bit is set to c onfigure the ptd0/dclk pin for sync processor dclk output. reset clears this bit. 1 = ptd0/dclk pin conf igured as dclk pin 0 = ptd0/dclk pin configur ed as standard i/o pin
input/output (i/o) ports port e mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor input/output (i/o) ports 249 17.7 port e port e is a standard 8- bit bidirectional port. 17.7.1 port e data register the port e data register (p te) contains a data latch for each of the eight port e pins. pte[7:0] ? port e data bits these read/write bits are software-p rogrammable. data direction of each port e pin is under the control of the corresponding bit in data direction register e. reset has no effect on port e data. 17.7.2 data direction register e data direction register e (ddre) dete rmines whether each port e pin is an input or an output. wr iting a logic 1 to a d dre bit enables the output buffer for the corresponding port e pi n; a logic 0 dis ables the output buffer. address: $0008 bit 7654321bit 0 read: pte7 pte6 pte5 pte4 pte3 pte2 pte1 pte0 write: reset: unaffected by reset figure 17-17. port e da ta register (pte) address: $0009 bit 7654321bit 0 read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset:00000000 figure 17-18. data direct ion register e (ddre)
input/output (i/o) ports technical data mc68hc908ld60 ? rev. 1.1 250 input/output (i/o) ports freescale semiconductor ddre[7:0] ? data dire ction register e bits these read/write bits control port e data direction. reset clears ddre[7:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note: avoid glitches on port e pi ns by writing to the port e data register before changing data direction regist er e bits fr om 0 to 1. figure 17-19 shows the port e i/o logic. figure 17-19. port e i/o circuit when bit ddrex is a l ogic 1, reading address $0008 reads the ptex data latch. when bit ddrex is a logic 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 17-6 summarizes the operation of the port e pins. table 17-6. port e pin functions ddre bit pte bit i/o pin mode accesses to ddre accesses to ptd read/write read write 0x (1) notes : 1. x = don?t care. input, hi-z (2) 2. hi-z = high impedance. ddre[7:0] pin pte[7:0] (3) 3. writing affects data register, but does not affect the input. 1 x output ddre[7:0] pte[7:0] pte[7:0] read ddre ($0009) write ddre ($0009) reset write pte ($0008) read pte ($0008) ptex ddrex ptex internal data bus
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor external interrupt (irq) 251 technical data ? mc68hc908ld60 section 18. external interrupt (irq) 18.1 contents 18.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 18.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 18.4.1 irq pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 18.5 irq status and contro l register (intscr) . . . . . . . . . . . . . . 255 18.6 irq module during break interrupts . . . . . . . . . . . . . . . . . . . 256 18.2 introduction the irq (external interrupt) module pr ovides a maskable interrupt input. 18.3 features features of the irq modul e include the following: a dedicated external interrupt pin, irq irq interrupt control bits hysteresis buffer programmable edge-only or edge and level interrupt sensitivity automatic interrupt acknowledge internal pullup resistor
external interrupt (irq) technical data mc68hc908ld60 ? rev. 1.1 252 external interrupt (irq) freescale semiconductor 18.4 functional description a logic 0 applied to the ex ternal interrupt pin ca n latch a cpu interrupt request. figure 18-1 shows the structure of the irq module. interrupt signals on the irq pin are latched into the irq latch. an interrupt latch remains set until on e of the following actions occurs: vector fetch ? a vector fetch au tomatically generates an interrupt acknowledge signal that clears the irq latch. software clear ? software can clea r the interrupt latch by writing to the acknowledge bit in the inte rrupt status and control register (intscr). writing a logic 1 to th e ack bit clears the irq latch. reset ? a reset automatically clears the interrupt latch. the external interrupt pin is fal ling-edge-triggered and is software- configurable to be either falli ng-edge or falling-edge and low-level- triggered. the mode bit in the intscr controls the triggering sensitivity of the irq pin. when the interrupt pin is edge-trigger ed only, the cpu interrupt request remains set until a vector fetch, software clear, or reset occurs. when the interrupt pin is both fallin g-edge and low-leve l-triggered, the cpu interrupt request remains set unt il both of the following occur: vector fetch or software clear return of the interr upt pin to logic 1 the vector fetch or software clear ma y occur before or af ter the interrupt pin returns to logic 1. as long as the pin is low, t he interrupt request remains pending. a reset will clear the la tch and the mode control bit, thereby clearing the interrup t even if the pin stays low. when set, the imask bit in the intscr mask a ll external interrupt requests. a latched interrupt request is not pres ented to the interrupt priority logic unless t he imask bit is clear.
external interrupt (irq) functional description mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor external interrupt (irq) 253 note: the interrupt mask (i) in the conditi on code register (ccr) masks all interrupt requests, including ex ternal interrupt requests. (see 9.6 exception control .) figure 18-1. irq module block diagram addr.register name bit 7654321bit 0 $001e irq status and control register (intscr) read: 0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 18-2. irq i/o register summary ack imask dq ck clr irq high interrupt to mode select logic irq ff request v dd mode voltage detect synchro- nizer irqf to cpu for bil/bih instructions vector fetch decoder internal address bus reset v dd i nternal pullup device irq
external interrupt (irq) technical data mc68hc908ld60 ? rev. 1.1 254 external interrupt (irq) freescale semiconductor 18.4.1 irq pin a logic 0 on the irq pin can latch an interrupt request into the irq latch. a vector fetch, software clear , or reset clears the irq latch. if the mode bit is set, the irq pin is both falling- edge-sensitive and low- level-sensitive. with mode set, both of the following actions must occur to clear irq: vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to cl ear the latch. software may generate the interrupt acknowledge si gnal by writing a logic 1 to the ack bit in the interrupt stat us and control register (intscr). the ack bit is useful in appl ications that poll the irq pin and require software to clear the irq la tch. writing to the ack bit prior to leaving an interrupt service r outine can also prevent spurious interrupts due to noise. setting ack does not af fect subsequent transitions on the irq pin. a falling edge that occurs after writing to the ack bi t latches another interrupt request. if t he irq mask bit, imask, is clear, the cpu loads the progr am counter with the vector address at locations $fffa and $fffb. return of the irq pin to logic 1 ? as long as the irq pin is at logic 0, irq remains active. the vector fetch or software cl ear and the retu rn of the irq pin to logic 1 may occur in any order. the interrupt request rema ins pending as long as the irq pin is at logic 0. a reset will clear the latch and the mode control bit, thereby cl earing the interrupt even if the pin stays low. if the mode bit is clear, the irq pin is falling-edge- sensitive only. with mode clear, a vector fetc h or software clear im mediately clears the irq latch. the irqf bit in the intscr register can be used to check for pending interrupts. the irqf bit is not affect ed by the imask bit, which makes it useful in applications wh ere polling is preferred. use the bih or bil in struction to read the logic level on the irq pin. note: when using the level-sensit ive interrupt trigger, av oid false interrupts by masking interrupt requests in the interrupt routine.
external interrupt (irq) irq status and control register (intscr) mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor external interrupt (irq) 255 18.5 irq status and co ntrol register (intscr) the irq status and control register (intscr) controls and monitors operation of the irq m odule. the intscr has t he following functions: shows the state of the irq flag clears the irq latch masks irq interrupt request controls triggering se nsitivity of the irq interrupt pin irqf ? irq flag this read-only status bi t is high when the irq interrupt is pending. 1 = irq interrupt pending 0 = irq interr upt not pending ack ? irq interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq latch. ack always reads as logic 0. reset clears ack. imask ? irq interrupt mask bit writing a logic 1 to this read/write bit disables irq interrupt requests. reset clears imask. 1 = irq interrupt requests disabled 0 = irq interrupt requests enabled mode ? irq edge/lev el select bit this read/write bit cont rols the triggering se nsitivity of the irq pin. reset clears mode. 1 = irq interrupt requests on falling edges and low levels 0 = irq interrupt reques ts on falling edges only address: $001e bit 7654321bit 0 read: 0000irqf0 imask mode write: ack reset:00000000 = unimplemented figure 18-3. irq status and control register (intscr)
external interrupt (irq) technical data mc68hc908ld60 ? rev. 1.1 256 external interrupt (irq) freescale semiconductor 18.6 irq module during break interrupts the system integration module (sim) co ntrols whether the irq latch can be cleared during the break state. the bcfe bit in the break flag control register (bfcr) enables software to clear the latches during the break state. (see section 9. system in tegration module (sim) .) to allow software to clear the irq la tch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared dur ing the break state, it remains cleared when the m cu exits the break state. to protect the latches during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writi ng to the ack bit in the irq status and control regi ster during the break state has no effect on the irq latch.
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor keyboard interrupt module (kbi) 257 technical data ? mc68hc908ld60 section 19. keyboard interrupt module (kbi) 19.1 contents 19.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 19.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 19.4 i/o pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 19.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .259 19.6 keyboard initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 19.7 i/o registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 19.7.1 keyboard status and control register. . . . . . . . . . . . . . . . 262 19.7.2 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . 263 19.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 19.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 19.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 19.9 keyboard module during break interrupts . . . . . . . . . . . . . . . 264 19.2 introduction the keyboard interrupt module (kbi ) provides eight independently maskable external interrupts whic h are accessible via pta0?pta7. when a port pin is enabled for keyboard interr upt function, an internal pullup device is also enabled on the pin.
keyboard interrupt module (kbi) technical data mc68hc908ld60 ? rev. 1.1 258 keyboard interrupt module (kbi) freescale semiconductor 19.3 features features of the keyboard inte rrupt module (kbi) include: eight keyboard interrupt pins with pullup devices separate keyboard in terrupt enable bits and one keyboard interrupt mask programmable edge-only or edge- and level- interrupt sensitivity exit from low-lower modes 19.4 i/o pins the eight keyboard interrupt pins are shar ed with standard port i/o pins. the full name of the kbi pins are listed in table 19-1 . the generic pin name appear in the te xt that follows. addr.register name bit 7654321bit 0 $004e keyboard status and control register (kbscr) read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 $004f keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 = unimplemented figure 19-1. kbi i/o register summary table 19-1. pin name conventions kbi generic pin name full mcu pin name pin selected for kbi function by kbiex bit in kbier kbi0?kbi7 pta0/kbi0?pta7/kbi7 kbie0?kbie7
keyboard interrupt module (kbi) functional description mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor keyboard interrupt module (kbi) 259 19.5 functional description figure 19-2. keyboard inte rrupt module block diagram writing to the kbie7?kbie0 bits in the keyboard interrupt enable register independently enables or disables each port a pin as a keyboard interrupt pin. enabling a keyboard interrupt pin al so enables its internal pullup device. a logic 0 applied to an enabled keyboar d interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched w hen one or more keyboard pins goes low after all were high. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. if the keyboard interrupt is e dge-sensitive only, a falling edge on a keyboard pin does not latch an in terrupt reques t if another keyboard pin is already low. to pr event losing an interrupt request on one pin because another pin is still low, software can disable the latter pin wh ile it is low. if the keyboard interrupt is falli ng edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modek bit is set, the keyboard interrupt pins ar e both falling edge- and low level-sensitive, and both of t he following actions must occur to clear a keyboard interrupt request: kbie0 kbie7 . . . dq ck clr v dd modek imaskk keyboard interrupt ff vector fetch decoder ackk internal bus reset kbi7 kbi0 synchronizer keyf keyboard interrupt request to pullup enable to pullup enable
keyboard interrupt module (kbi) technical data mc68hc908ld60 ? rev. 1.1 260 keyboard interrupt module (kbi) freescale semiconductor vector fetch or software clear ? a vector fetc h generates an interrupt acknowledge signal to clear the interrupt request. software may generate the inte rrupt acknowle dge signal by writing a logic 1 to t he ackk bit in the keyboa rd status and control register (kbscr). the a ckk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine also can prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ackk bi t latches another inte rrupt request. if the keyboard interrupt mask bit, imask k, is clear, the cpu loads the program counter with the vector address at locations $ffe2 and $ffe3. return of all enabled keyboard interr upt pins to logic 1 ? as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the key board interrupt pin is falling-edge- sensitive only. with mo dek clear, a vector fetc h or software clear immediately clears the ke yboard interrupt request. reset clears the keyboard interrupt request and the modek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the ke yboard status and control register can be used to see if a pending inte rrupt exists. the keyf bit is not affected by the keyboard interrupt mask bit (imaskk) which makes it useful in applications wh ere polling is preferred. to determine the logi c level on a keyboard inte rrupt pin, use the data direction register to configure the pin as an input and read the data register. note: setting a keyboard interrupt enable bi t (kbiex) forces the corresponding keyboard interrupt pin to be an inpu t, overriding t he data direction register. however, the dat a direction register bi t must be a logic 0 for software to read the pin.
keyboard interrupt module (kbi) keyboard initialization mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor keyboard interrupt module (kbi) 261 19.6 keyboard initialization when a keyboard interrupt pin is enab led, it takes time for the pullup device to reach a logic 1. therefore, a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by se tting the imaskk bit in the keyboard status and control register. 2. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edg e-triggered pin can be acknowledged immediately after enabling the pin. an interrupt si gnal on an edge- and level-triggered interrupt pin must be acknowledged afte r a delay that depends on the external load. another way to avoi d a false interrupt: 1. configure the keyboard pins as outputs by setting the appropriate ddra bits in data di rection register a. 2. write logic 1s to the appropriate port a data register bits. 3. enable the kbi pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 19.7 i/o registers these registers control a nd monitor operation of the keyboard module: keyboard status and cont rol register (kbscr) keyboard interrupt enabl e register (kbier)
keyboard interrupt module (kbi) technical data mc68hc908ld60 ? rev. 1.1 262 keyboard interrupt module (kbi) freescale semiconductor 19.7.1 keyboard status and control register flags keyboard interrupt requests acknowledges keyboard interrupt requests masks keyboard interrupt requests controls keyboard interrupt triggering sensitivity keyf ? keyboard flag bit this read-only bit is set when a ke yboard interrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending ackk ? keyboard acknowledge bit writing a logic 1 to th is write-only bit clears the keyboard interrupt request. ackk always reads as logic 0. rese t clears ackk. imaskk ? keyboard interrupt mask bit writing a logic 1 to th is read/write bit prev ents the output of the keyboard interrupt mask from gene rating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek ? keyboard tri ggering sensitivity bit this read/write bit controls the tri ggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt reques ts on falling edges and low levels 0 = keyboard interrupt requests on falling edges only address: $004e bit 7654321bit 0 read: 0000 keyf 0 imaskk modek write: ackk reset:00000000 = unimplemented figure 19-3. keyboard status and control regi ster (kbscr)
keyboard interrupt module (kbi) low-power modes mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor keyboard interrupt module (kbi) 263 19.7.2 keyboard interrupt enable register the keyboard interrupt enabl e register enables or disables each port a pin to operate as a ke yboard interrupt pin. kbie7?kbie0 ? keyboard interrupt enable bits each of these read/write bits enables the corres ponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = ptax/kbix pin enabled as keyboard interrupt pin 0 = ptax/kbix pin not enabled as keyboa rd interrupt pin 19.8 low-power modes the wait and stop in structions put the mcu in low-power- consumption standby modes. 19.8.1 wait mode the keyboard interrupt module remains ac tive in wait m ode. clearing the imaskk bit in the keyboar d status and control r egister enables keyboard interrupt requests to brin g the mcu out of wait mode. 19.8.2 stop mode the keyboard interrupt module remain s active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to br ing the mcu out of stop mode. address: $004f bit 7654321bit 0 read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset:00000000 figure 19-4. keyboard interr upt enable register (kbier)
keyboard interrupt module (kbi) technical data mc68hc908ld60 ? rev. 1.1 264 keyboard interrupt module (kbi) freescale semiconductor 19.9 keyboard module during break interrupts the system integration module (sim) controls whether the keyboard interrupt latch can be cleared during t he break state. the bcfe bit in the break flag control register (bfcr) enabl es software to clear status bits during the break state. to allow software to clear the key board interrupt la tch during a break interrupt, write a logic 1 to the bcfe bit. if a latch is cleared during the break state, it remains cleared w hen the mcu exits the break state. to protect the latch during the break st ate, write a logi c 0 to the bcfe bit. with bcfe at logi c 0 (its default state), writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break stat e has no effect. (see 19.7.1 keyboard status and control register .)
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor computer operating properly (cop) 265 technical data ? mc68hc908ld60 section 20. computer operating properly (cop) 20.1 contents 20.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 20.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .266 20.4 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 20.4.1 oscxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 20.4.2 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 20.4.3 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 20.4.4 power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 20.4.5 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 20.4.6 reset vector fetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 20.4.7 copd (cop disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 20.4.8 coprs (cop rate sele ct) . . . . . . . . . . . . . . . . . . . . . . . . 268 20.5 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 20.6 interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 20.7 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 20.8 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 20.8.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 20.8.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 20.9 cop module during break mode . . . . . . . . . . . . . . . . . . . . . . 270 20.2 introduction the computer operating properly (cop ) module contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runa way code. prevent a cop reset by clearing the cop counter periodically. the cop module can be disabled through the copd bit in the config register.
computer operating properly (cop) technical data mc68hc908ld60 ? rev. 1.1 266 computer operating properly (cop) freescale semiconductor 20.3 functional description figure 20-1 shows the structure of the cop module. figure 20-1. cop block diagram the cop counter is a free-running 6- bit counter preceded by a 12-bit prescaler counter. if not cleared by software, the cop counter overflows and generates an asynchr onous reset after 2 18 ?2 4 or 2 13 ?2 4 oscxclk cycles, depending on the state of the co p rate select bit, coprs, in configuration register 1. with a 2 18 ?2 4 oscxclk cycle overflow option, a 24 mhz crystal gives a co p timeout period of 10.922ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by cleari ng the cop count er and stages 12 through 5 of the prescaler. note: service the cop immediately after re set and before entering or after exiting stop mode to guarantee the ma ximum time before the first cop counter overflow. copctl write oscxclk reset vector fetch reset circuit reset status register internal reset sources 12-bit cop prescaler clear all stages 6-bit cop counter cop disable reset copctl write clear copen (from sim) cop counter cop clock cop timeout stop instruction (copd from config) cop rate sel (coprs from config) clear stages 5?12
computer operating properly (cop) i/o signals mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor computer operating properly (cop) 267 a cop reset pulls the rst pin low for 32 oscxcl k cycles and sets the cop bit in the sim reset status register (srsr). in monitor mode, the cop is disabled if the rst pin or the irq is held at v tst . during the br eak state, v tst on the rst pin disables the cop. note: place cop clearing instructions in the main program and not in an interrupt subroutine. su ch an interrupt subrout ine could keep the cop from generating a reset even while the main pr ogram is not working properly. 20.4 i/o signals the following paragraphs descri be the signals shown in figure 20-1 . 20.4.1 oscxclk oscxclk is the crystal oscillator output signal . oscxclk frequency is equal to the crystal frequency. 20.4.2 stop instruction the stop instruction cl ears the cop prescaler. 20.4.3 copctl write writing any value to the cop c ontrol register (copctl) (see 20.5 cop control register ) clears the cop counter a nd clears bits 12 through 5 of the prescaler. reading the cop cont rol register retu rns the low byte of the reset vector. 20.4.4 power-on reset the power-on reset (por) circuit clears the cop prescaler 4096 oscxclk cycles after power-up.
computer operating properly (cop) technical data mc68hc908ld60 ? rev. 1.1 268 computer operating properly (cop) freescale semiconductor 20.4.5 internal reset an internal reset clears the co p prescaler and the cop counter. 20.4.6 reset vector fetch a reset vector fetch occurs when the vector addres s appears on the data bus. a reset vector fetch clears the cop prescaler. 20.4.7 copd (cop disable) the copd signal reflec ts the state of the cop di sable bit (copd) in the config register. (see figure 20-2 .) 20.4.8 coprs (cop rate select) the coprs signal reflects the state of the cop ra te select bit (coprs) in the config register. (see figure 20-2 .) coprs ? cop rate select bit coprs selects the cop timeout period. rese t clears coprs. 1 = cop timeout period is 2 13 ? 2 4 oscxclk cycles 0 = cop timeout period is 2 18 ? 2 4 oscxclk cycles copd ? cop disable bit copd disables the cop module. 1 = cop module disabled 0 = cop module enabled address: $001f bit 7654321bit 0 read: 0000 ssrec coprs stop copd write: reset:00000000 = unimplemented figure 20-2. configurat ion register (config)
computer operating properly (cop) cop control register mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor computer operating properly (cop) 269 20.5 cop control register the cop control register is locat ed at address $ffff and overlaps the reset vector. writing any value to $ffff clears t he cop counter and starts a new timeout per iod. reading location $ffff returns the low byte of the reset vector. 20.6 interrupts the cop does not generate cpu interrupt requests. 20.7 monitor mode when monitor mode is entered with v tst on the irq pin, the cop is disabled as long as v tst remains on the irq pin or the rst pin. when monitor mode is enter ed by having blank rese t vectors and not having v tst on the irq pin, the cop is automatic ally disabled until a por occurs. 20.8 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. address: $ffff bit 7654321bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 20-3. cop cont rol register (copctl)
computer operating properly (cop) technical data mc68hc908ld60 ? rev. 1.1 270 computer operating properly (cop) freescale semiconductor 20.8.1 wait mode the cop remains active during wait mode. to prevent a cop reset during wait mode, periodi cally clear the cop counter in a cpu interrupt routine. 20.8.2 stop mode stop mode turns off the oscxclk input to the cop and clears the cop prescaler. service the co p immediately before ent ering or after exiting stop mode to ensure a full cop timeout period a fter entering or exiting stop mode. to prevent inadvertently turning off t he cop with a stop instruction, a configuration option is av ailable that disables the stop instruction. when the stop bit in the config uration register has the stop instruction is disabled, execution of a stop in struction results in an illegal opcode reset. 20.9 cop module during break mode the cop is disabled during a break interrupt when v tst is present on the rst pin.
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor break module (brk) 271 technical data ? mc68hc908ld60 section 21. break module (brk) 21.1 contents 21.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 21.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 21.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .272 21.4.1 flag protection during break interr upts . . . . . . . . . . . . . . . 274 21.4.2 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . .274 21.4.3 tim during break interr upts . . . . . . . . . . . . . . . . . . . . . . . . 274 21.4.4 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . 274 21.5 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 21.5.1 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 21.5.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .275 21.6 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 21.6.1 break status and control register. . . . . . . . . . . . . . . . . . . 275 21.6.2 break address register s . . . . . . . . . . . . . . . . . . . . . . . . . . 276 21.6.3 sim break status regi ster . . . . . . . . . . . . . . . . . . . . . . . . . 276 21.6.4 sim break flag control register . . . . . . . . . . . . . . . . . . . . 278 21.2 introduction this section describes the break module. the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program.
break module (brk) technical data mc68hc908ld60 ? rev. 1.1 272 break module (brk) freescale semiconductor 21.3 features features of the br eak module include: accessible input/output (i/o) regi sters during the break interrupt cpu-generated break interrupts software-generated break interrupts cop disabling during break interrupts 21.4 functional description when the internal address bus matches the value written in the break address registers, the br eak module issues a breakpoint signal to the cpu. the cpu then loads the instruct ion register with a software interrupt instruction (swi) afte r completion of the current cpu instruction. the program count er vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: a cpu-generated address (the addr ess in the program counter) matches the contents of th e break address registers. software writes a logic 1 to the brka bit in the break status and control register. when a cpu-generated addre ss matches the contents of the break address registers, th e break interrupt begins af ter the cpu completes its current instruction. a return-from-inter rupt instruction (r ti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 21-1 shows the structure of the break module.
break module (brk) functional description mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor break module (brk) 273 figure 21-1. break module block diagram iab15?iab8 iab7?iab0 8-bit comparator 8-bit comparator control break address register low break address register high iab15?iab0 break addr.register name bit 7654321bit 0 $fe00 sim break status register (sbsr) read: rrrrrr sbsw r write: note reset: 0 $fe03 sim break flag control register (sbfcr) read: bcferrrrrrr write: reset: 0 $fe0c break address register high (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 $fe0d break address register low (brkl) read: bit 7654321bit 0 write: reset:00000000 $fe0e break status and control register (brkscr) read: brke brka 000000 write: reset:00000000 note: writing a logic 0 clears sbsw. = unimplemented r = reserved figure 21-2. break modul e i/o register summary
break module (brk) technical data mc68hc908ld60 ? rev. 1.1 274 break module (brk) freescale semiconductor 21.4.1 flag protection during break interrupts the bcfe bit in the sim break flag control register (sbfcr) enables software to clear status bi ts during the break state. 21.4.2 cpu during break interrupts the cpu starts a br eak interrupt by: loading the instruction regist er with the swi instruction loading the program count er with $fffc and $fffd ($fefc and $fefd in monitor mode) the break interrupt begins after completion of t he cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. 21.4.3 tim during break interrupts a break interrupt stops the timer counters. 21.4.4 cop during break interrupts the cop is disabled during a break interrupt when v tst is present on the rst pin. 21.5 low-power modes the wait and stop in structions put the mcu in low power- consumption standby modes. 21.5.1 wait mode if enabled, the break module is active in wait mode. in the break routine, the user can subtract one from the re turn address on the stack if sbsw is set (see section 9. system in tegration module (sim) ). clear the sbsw bit by writi ng logic 0 to it.
break module (brk) break module registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor break module (brk) 275 21.5.2 stop mode a break interrupt causes exit from stop mode and sets the sbsw bit in the break status register. 21.6 break module registers these registers control and monitor operation of the break module: break status and cont rol register (brkscr) break address regi ster high (brkh) break address regi ster low (brkl) sim break status register (sbsr) sim break flag con trol register (sbfcr) 21.6.1 break status and control register the break status and control register (brkscr) contai ns break module enable and status bits. brke ? break enable bit this read/write bit enabl es breaks on break address register matches. clear brke by writing a logic 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16 -bit address match 0 = breaks disabled on 16-bit address match address: $fe0e bit 7654321bit 0 read: brke brka 000000 write: reset:00000000 = unimplemented figure 21-3. break status an d control register (brkscr)
break module (brk) technical data mc68hc908ld60 ? rev. 1.1 276 break module (brk) freescale semiconductor brka ? break active bit this read/write status and control bit is se t when a break address match occurs. writing a logic 1 to brka generates a break interrupt. clear brka by writing a logic 0 to it before exiting the break routine. reset clears the brka bit. 1 = (when read) br eak address match 0 = (when read) no break address match 21.6.2 break address registers the break address register s (brkh and brkl) contai n the high and low bytes of the desired brea kpoint address. reset clears the break address registers. 21.6.3 sim break status register the sim break status register (sbsr) contains a flag to indicate that a break caused an exit from wait mode. the flag is useful in applications requiring a return to wait mode a fter exiting from a break interrupt. address: $fe0c bit 7654321bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset:00000000 figure 21-4. break addres s register high (brkh) address: $fe0d bit 7654321bit 0 read: bit 7654321bit 0 write: reset:00000000 figure 21-5. break addr ess register low (brkl)
break module (brk) break module registers mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor break module (brk) 277 sbsw ? sim break stop/wait bit this status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. clear sbsw by writing a logic 0 to it. re set clears sbsw. 1 = stop mode or wa it mode was exited by break interrupt 0 = stop mode or wait mode was not exited by break interrupt sbsw can be read within the break interrupt routine. the user can modify the return address on the st ack by subtractin g one from it. the following code is an example. address: $fe00 bit 7654321bit 0 read: rrrrrr sbsw r write: note reset: 0 note: writing a logic 0 clears sbsw. r=reserved figure 21-6. sim break stat us register (sbsr) ; ; ; this code works if the h register has been pushed onto the stack in the break service routine software. this code should be executed at the end of the break service routine software. hibyte equ 5 lobyte equ 6 ; if not sbsw, do rti brclr sbsw,sbsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ;if returnlo is not zero, bne dolo ;then just decrement low byte. dec hibyte,sp ;else deal with high byte, too. dolo dec lobyte,sp ;point to wait/stop opcode. return pulh rti ;restore h register.
break module (brk) technical data mc68hc908ld60 ? rev. 1.1 278 break module (brk) freescale semiconductor 21.6.4 sim break flag control register the sim break flag control register (s bfcr) contains a bit that enables software to clear status bits wh ile the mcu is in a break state. bcfe ? break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to cl ear status bits during the break state, t he bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break address: $fe03 bit 7654321bit 0 read: bcferrrrrrr write: reset: 0 r=reserved figure 21-7. sim break flag c ontrol register (sbfcr)
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor electrical specifications 279 technical data ? mc68hc908ld60 section 22. electrical specifications 22.1 contents 22.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 22.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . 280 22.4 functional operating range. . . . . . . . . . . . . . . . . . . . . . . . . . 281 22.5 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 22.6 dc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . 282 22.7 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 22.8 timer interface module characterist ics . . . . . . . . . . . . . . . . . 283 22.9 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 22.10 adc electrical characteri stics . . . . . . . . . . . . . . . . . . . . . . . . 284 22.11 sync processor timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 22.12 ddc12ab/mmiic timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 22.12.1 ddc12ab/mmiic interface input signal timing . . . . . . . . 285 22.12.2 ddc12ab/mmiic interface output signal timing . . . . . . . 285 22.13 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . 286
electrical specifications technical data mc68hc908ld60 ? rev. 1.1 280 electrical specifications freescale semiconductor 22.2 introduction this section contains electrical and timing specifications. 22.3 absolute maximum ratings maximum ratings are t he extreme limits to which the mcu can be exposed without perman ently damaging it. note: this device is not guar anteed to operate properly at the maximum ratings. refer to 22.6 dc electrical characteristics for guaranteed operating conditions. note: this device contains circ uitry to protect the i nputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid applic ation of any voltage higher than maximum-rated voltages to this hi gh-impedance circui t. for proper operation, it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd . reliability of operation is enhanced if unused inputs are co nnected to an appropriate logic voltage level (for example, either v ss or v dd .) table 22-1. absolute maximum ratings characteristic (1) notes : 1. voltages referenced to v ss . symbol value unit supply voltage v dd ?0.3 to +3.9 v input voltage v in v ss ?0.3 to v dd +0.3 v input voltage, +5v pins iicsda, iicscl, ddcsda, dcscl, hsync, vsync v hin v ss ?0.3 to +5.5 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg ?55 to +150 c maximum current out of v ss i mvss 80 ma maximum current into v dd i mvdd 80 ma
electrical specifications functional operating range mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor electrical specifications 281 22.4 functional operating range 22.5 thermal characteristics table 22-2. operating range characteristic symbol value unit operating temperature range t a 0 to +85 c operating voltage range v dd 3.0 to 3.6 v table 22-3. thermal characteristics characteristic symbol value unit thermal resistance qfp (64 pins) ja 70 c/w i/o pin power dissipation p i/o user determined w power dissipation (1) notes : 1. power dissipation is a function of temperature. p d p d = (i dd x v dd ) + p i/o = k/(t j + 273 c) w constant (2) 2. k is a constant unique to the devi ce. k can be determined for a known t a and measured p d. with this value of k, p d and t j can be determined for any value of t a . k p d (t a + 273 c) + p d 2 ja w/ c average junction temperature t j t a + (p d ja ) c maximum junction temperature t jm 100 c
electrical specifications technical data mc68hc908ld60 ? rev. 1.1 282 electrical specifications freescale semiconductor 22.6 dc electrical characteristics table 22-4. dc elect rical characteristics characteristic (1) notes : 1. v dd = 3.0 to 3.6 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol min typ (2) 2. typical values reflect average measur ements at midpoint of voltage range, 25 c only. max unit output high voltage (i load = ?2.0ma) all output pins v oh 2.4 ? ? v output low voltage (i load = 1.6ma) all output pins v ol ??0.4v input high voltage all ports (except ptd4?ptd7), irq , rst , osc1 for +5v rated pins hsync, vsync, iicsda, iicscl, ddcsda, ddcscl v ih 0.7 v dd 2.0 ? ? v dd 5.5 v input low voltage all ports (except ptd4?ptd7), irq , rst , osc1 for +5v rated pins hsync, vsync, iicsda, iicscl, ddcsda, ddcscl v il v ss v ss ? ? 0.2 v dd 0.8 v v dd supply current run, pll off, f op = 6.0 mhz (3) wait, pll off, f op = 6.0 mhz (4) stop (5) 0 c to +85 c 3. run (operating) i dd measured using external square wave clock source. all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. cl = 20 pf on osc2. all ports c onfigured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f oscxclk = 24mhz); all inputs 0.2 v from rail; no dc loads; less than 100 pf on all outputs. c l = 20 pf on osc2; all ports configured as inputs; osc2 capacitance linearly affects wait i dd . 5. stop i dd osc1 grounded, no port pins sourcing current. i dd ? ? ? 9 4 100 16 8 200 ma ma a i/o ports hi-z leakage current i il ?? 10 a input current all input pins (except below pins) hsync, vsync i in ? ? ? ? 1 2 a capacitance ports (as input or output) c out c in ? ? ? ? 12 8 pf por re-arm voltage (6) 6. maximum is highest vo ltage that por is guaranteed. v por 0?100mv por rise time ramp rate (7) 7. if minimum v dd is not reached before the inter nal por reset is released, rst must be driven low externally until minimum v dd is reached. r por 0.035 ? ? v/ms monitor mode entry voltage v tst v dd + 1.7 ? 6 v pull-up resistor kbi0?kbi7, rst , irq r pu 30 45 60 k ? low-voltage inhibit, trip falling voltage v tripf 2.45 v low-voltage inhibit, trip rising voltage v tripr 2.6 v low-voltage inhibit reset/recover hysteresis v hys ?150?mv
electrical specifications control timing mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor electrical specifications 283 22.7 control timing 22.8 timer interface module characteristics 22.9 oscillator characteristics table 22-5. control timing characteristic (1) notes : 1. v dd = 3.0 to 3.6 vdc, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit internal operating frequency (2) 2. some modules may require a minimum freq uency greater than dc for proper operation; see appropriate table for this information. f op ?6mhz rst input pulse width low (3) 3. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. t irl 50 ? ns table 22-6. tim characteristics characteristic symbol min max unit input capture pulse width t tih, t til 125 ? ns input clock pulse width t tch, t tcl (1/f op ) + 5 ? ns table 22-7. oscillat or characteristics characteristic symbol min typ max unit crystal frequency (1) notes : 1. the sync processor module is designed to function at f oscxclk = 24mhz. f oscxclk ?24 ? mhz external clock reference frequency (1), (2) 2. no more than 10% duty cycle deviation from 50% f oscxclk dc 24 ? mhz crystal fixed capacitance (3) c 1 ? 15 ?pf crystal tuning capacitance (3) c 2 ? 15 ?pf feedback bias resistor r b ?2 ? m ? series resistor (3) 3. not required for high frequency crystals r s ?0 ? ?
electrical specifications technical data mc68hc908ld60 ? rev. 1.1 284 electrical specifications freescale semiconductor 22.10 adc electrical characteristics 22.11 sync processor timing table 22-8. adc elect rical characteristics characteristic (1) notes : 1. v dd = 3.0 to 3.6 vdc, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. symbol min max unit comments supply voltage v ddad 3.0 3.6 v v dd 10% input voltages v adin 0 v dd v resolution b ad 88bits absolute accuracy a ad 1 2 lsb includes quantization adc internal clock f adic 0.5 1.048 mhz t aic = 1/f adic , tested only at 1 mhz conversion range r ad v ss v dd v power-up time t adpu 16 t aic cycles conversion time t adc 16 17 t aic cycles sample time (2) 2. source impedances greater than 10 k ? adversely affect internal rc charging time during input sampling. t ads 5? t aic cycles zero input reading (3) 3. zero-input/full-scale reading requires sufficien t decoupling measures for accurate conversions. z adi 00 02 hex full-scale reading (3) f adi fd ff hex input capacitance c adi ? 8 pf not tested input leakage (4) : port c 4. the external system error caused by input leakage current is approximately equal to the product of r source and input current. ?? 1 a table 22-9. sync processor timing characteristic (1) notes : 1. v dd = 3.0 to 3.6 vdc, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit vsync input sync pulse t vi.sp 82048 s hsync input sync pulse t hi.sp 0.1 6 s vsync to vsynco delay (8pf loading) t vvd 30 40 s hsync to hsynco delay (8pf loading) t hhd 30 40 s de set-up time of dclk t desu 4? s de hold time of dclk t dehd 4? s
electrical specifications ddc12ab/mmiic timing mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor electrical specifications 285 22.12 ddc12ab/mmiic timing figure 22-1. mmii c signal timings 22.12.1 ddc12ab/mmiic interface input signal timing 22.12.2 ddc12ab/mmiic interface output signal timing table 22-10. ddc12ab/mmiic interface input signal timing characteristic (1) notes : 1. v dd = 3.0 to 3.6 vdc, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit start condition hold time t hd.sta 2? t cyc clock low period t low 4? t cyc clock high period t high 4? t cyc data set-up time t su.dat 250 ? ns data hold time t hd.dat 0?ns start condition set-up time (for repeated start condition only) t su.sta 2? t cyc stop condition set-up time t su.sto 2? t cyc table 22-11. ddc12ab/ mmiic interface ou tput signal timing characteristic (1) notes : 1. v dd = 3.0 to 3.6 vdc, v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v dd , unless otherwise noted. symbol min max unit sda/scl rise time (2) 2. with 200pf loading on the sda/scl pins. t r ?1 s sda/scl fall time t f ? 300 ns data set-up time t su.dat t low ?ns data hold time t hd.dat 0?ns sda scl t hd.sta t low t high t su.dat t hd.dat t su.sta t su.sto
electrical specifications technical data mc68hc908ld60 ? rev. 1.1 286 electrical specifications freescale semiconductor 22.13 flash memory characteristics table 22-12. flash memory electrical characteristics characteristic symbol min max unit program bus clock frequency ? 1 ? mhz flash block size $0c00?$0fff $1000?f9ff ? ? 128 512 bytes bytes flash programming size ? 64 bytes read bus clock frequency f read (1) notes : 1. f read is defined as the frequency range for which the flash memory can be read. 32k 6m hz page erase time t erase (2) 2. if the page erase time is longer than t erase (min), there is no erase-disturb, but it reduces the endurance of the flash memory. 10 ? ms mass erase time t merase (3) 3. if the mass erase time is longer than t merase (min), there is no erase-disturb, bu t it reduces the endurance of the flash memory. 10 ? ms pgm/erase to hven set up time t nvs 5? s high-voltage hold time t nvh 5? s high-voltage hold time (mass erase) t nvhl 100 ? s program hold time t pgs 20 ? ns program time t prog 20 40 s return to read time t rcv (4) 4. t rcv is defined as the time it n eeds before the flash can be read after turning off the high voltage charge pump, by clearing hven to logic 0. 1? s cumulative program hv period 4,7616 bytes array 13k-bytes array t hv (5) t hv1 (6) 5. t hv is defined as the cumulative high voltage programming time to the same row before next erase. t hv must satisfy this condition: t nvs + t nvh + t pgs + (t prog 64) t hv max. 6. t hv1 is the t hv spec for 13k-bytes array ? ? 6 3 ms ms row erase endurance (7) 7. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ? 10k ? cycles row program endurance (8) 8. the minimum row endurance value specifies each row of the flash memory is guaranteed to work for at least this many erase / program cycles. ? 10k ? cycles data retention time (9) 9. the flash is guaranteed to retain data over the entire operating temperature range for at least the minimum time specified. ?10?years
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor mechanical specifications 287 technical data ? mc68hc908ld60 section 23. mechanical specifications 23.1 contents 23.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 23.3 64-pin plastic quad flat pack (qfp) . . . . . . . . . . . . . . . . . . . 288 23.2 introduction this section gives t he dimensions for: 64-pin plastic quad fl at pack (case 840b-01) figure 23-1 shows the latest package dra wing at the time of this publication. to make sure that you have the latest package specifications, please visi t the freescale website at http://freescale.com. follow the world wide web on-line inst ructions to retrieve the current mechanical specifications.
mechanical specifications technical data mc68hc908ld60 ? rev. 1.1 288 mechanical specifications freescale semiconductor 23.3 64-pin plastic quad flat pack (qfp) figure 23-1. 64-pin plasti c quad flat pack (qfp) l l ?a? ?b? detail a ?d? b a s v detail a p b b d ?a?, ?b?, ?d? c ?c? e h g m m detailc seating plane datum plane 1 16 ?h? 0.01 (0.004) r detail c datum plane ?h? t u q k w x s a?b m 0.20 (0.008) d s h s a?b m 0.20 (0.008) d s c 0.05 (0.002) a?b s a?b m 0.20 (0.008) d s c 0.05 (0.002) a?b s a?b m 0.20 (0.008) d s h 48 33 s a?b m 0.02 (0.008) d s c n f j base metal 32 49 17 64 dim min max min max inches millimeters a 13.90 14.10 0.547 0.555 b 13.90 14.10 0.547 0.555 c 2.15 2.45 0.085 0.096 d 0.30 0.45 0.012 0.018 e 2.00 2.40 0.079 0.094 f 0.30 0.40 0.012 0.016 g 0.80 bsc 0.031 bsc h ? 0.25 ? 0.010 j 0.13 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 12.00 ref 0.472 ref m 5 10 5 10 n 0.13 0.17 0.005 0.007 p 0.40 bsc 0.016 bsc q 0 7 0 7 r 0.13 0.30 0.005 0.012 s 16.95 17.45 0.667 0.687 t 0.13 ? 0.005 ? u 0 ?0 ? v 16.95 17.45 0.667 0.687 w 0.35 0.45 0.014 0.018 x 1.6 ref 0.063 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ?h? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ?a?, ?b? and ?d? to be determined at datum plane ?h?. 5. dimensions s and v to be determined at seating plane ?c?. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ?h?. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) per side. total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. section b?b
mc68hc908ld60 ? rev. 1.1 technical data freescale semiconductor ordering information 289 technical data ? mc68hc908ld60 section 24. ordering information 24.1 contents 24.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 24.3 mc order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 24.2 introduction this section contains ordering numbers for the mc68hc908ld60. 24.3 mc order numbers table 24-1. mc order numbers mc order number (1) notes : 1. i = operating temperature range: 0 c to +85 c fu = quad flat pack package operating temperature range MC68HC908LD60IFU 64-pin qfp 0 c to +85 c
ordering information technical data mc68hc908ld60 ? rev. 1.1 290 ordering information freescale semiconductor

how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the arm powered logo is a registered trademark of arm limited. arm7tdmi-s is a trademark of arm limited. java and all other java-based marks are trademarks or registered trademarks of sun microsystems, inc. in the u.s. and other countries. the bluetooth trademarks are owned by their proprietor and used by freescale semiconductor, inc. under license. ? freescale semiconductor, inc. 2005. all rights reserved. rev. 1.1 mc68hc908ld60/d august 16, 2005

▲Up To Search▲

Price & Availability of MC68HC908LD60IFU

	To Download MC68HC908LD60IFU Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .